The present disclosure describes a semiconductor device having a dielectric fin structure. The semiconductor device includes a channel structure on a substrate and a dielectric fin structure on the substrate and adjacent to the channel structure. The channel structure extends along a first direction. The dielectric fin structure includes a stiff dielectric material and extends along a second direction parallel to the first direction. The semiconductor device further includes an isolation structure extending through the channel structure. The isolation structure is in contact with the dielectric fin structure.

An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.

An example semiconductor device includes a substrate, a channel layer disposed on the substrate, a gate structure surrounding the channel layer, source/drain patterns connected with both sides of the channel layer, a lower wiring structure disposed below the substrate, and an insulating pattern extending through the substrate and disposed between the source/drain patterns below the gate structure. The insulating pattern includes a sub-insulating pattern disposed below the gate structure and a main insulating pattern disposed between the sub-insulating pattern and the lower wiring structure. The sub-insulating pattern and the main insulating pattern include different insulating materials.

The present disclosure describes a semiconductor device having a contact structure isolated from a source/drain structure. The semiconductor structure includes a gate structure on a substrate, first and second source/drain (S/D) structures on opposite sides of the gate structure, an isolation layer on the second S/D structure, a third S/D structure adjacent to and separate from the second S/D structure, and a S/D contact structure on the isolation layer and the third S/D structure. The isolation layer separates the S/D contact structure from the second S/D structure.

A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

A semiconductor device includes a lower interlayer insulating layer including a first surface and a second surface that are opposite to each other in a first direction; a plurality of active patterns disposed on the first surface of the lower interlayer insulating layer; a gate structure disposed on the first surface of the lower interlayer insulating layer; a source/drain pattern connected to the plurality of active patterns; a lower conductive layer that is disposed on the second surface of the lower interlayer insulating layer and includes a first surface and a second surface; a lower source/drain contact protruding from the lower conductive layer in the first direction and connected to the source/drain pattern; and a contact separation pattern that penetrates the lower conductive layer and is in contact with the lower interlayer insulating layer.

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.

An exemplary flowable chemical vapor deposition method includes depositing a flowable dielectric material over a substrate, ultraviolet curing the flowable dielectric material, and annealing the ultraviolet cured, flowable dielectric material. The flowable dielectric material fills a space between a first gate structure and a second gate structure. An ultraviolet power of the ultraviolet curing is greater than about 80%, and an annealing temperature of the annealing is less than about 500 C. A thickness of the flowable dielectric material deposited over tops of the first gate structure and the second gate structure is less than about 200 nm. The ultraviolet power, the temperature, and an as-deposited thickness may be selected based on germanium pile up characteristics expected at an inner spacer/source/drain interface.