Semiconductor devices and methods for forming the semiconductor devices using diffusion cap layers are provided. The semiconductor devices include a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers, and a plurality of diffusion cap layers disposed between and separating the plurality of semiconductor layers and the gate structure. In some embodiments, the plurality of diffusion cap layers function as diffusion barriers for the plurality of semiconductor layers.

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Disclosed herein are methods for direct backside contact formation. In some embodiments, a method may include providing a stack of layers defining a front side and a backside, wherein the front side comprises one or more devices, and forming a plurality of vias in the backside, wherein each via of the plurality of vias extends to a source/drain. The method may further include performing a dopant implant to the backside including into the plurality of vias, wherein the dopant implant is performed at a temperature greater than 300 C., forming a silicide region within each of the source/drains, and forming a backside contact within each of the plurality of vias, wherein the backside contact is formed over the silicide region.

A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.

The disclosed technology generally relates to a complementary field effect transistor (CFET) structure. In one aspect, the CFET structure includes at least one CFET element having a first transistor structure, and a second transistor structure which is arranged above the first transistor structure and which includes a source and/or drain structure. The CFET structure further includes a power rail arranged below the first transistor structure of the at least one CFET element, and a power routing line arranged above the second transistor structure of the at least one CFET element. The power routing line is electrically connected to the source and/or drain structure of the second transistor structure from the top. The at least one CFET element further has a tap connection structure which is arranged to electrically connect the power rail with the source and/or drain structure of the second transistor structure. The tap connection structure is arranged to bypass the first transistor structure on one side.

A substrate processing method includes an outer etching step of etching an outer portion by supplying an etching liquid to a substrate including an end surface, an inner surface forming a gap which has a width smaller than a depth of the gap and is open at the end surface, and the etching target having an outer portion disposed outside the gap and an inner portion disposed in the gap, and an inner etching step of etching the inner portion with a mixed etching liquid which has entered the gap by supplying, to the substrate, the mixed etching liquid which is an etching liquid obtained by dissolving a low-surface-tension liquid having a surface tension smaller than a surface tension of the etching liquid, after the outer portion of the etching target is etched.