A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

An integrated circuit device includes: a fin-type active area extending in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active area; a source/drain area arranged on the fin-type active area; a gate dielectric layer disposed on the gate line; a source/drain contact arranged on the source/drain area; a via contact integrally connected to the source/drain contact and protruding in a vertical direction; a gate contact plug integrally connected to the gate line and protruding in the vertical direction; a first wiring layer electrically connected to the via contact and the gate contact plug; and a via rail connected to the first wiring layer, and extending in the first horizontal direction at a vertical level that is lower than a vertical level of the first wiring layer.

A method for making a semiconductor device may include forming a stack of alternating gate and nanostructure layers above a substrate, and forming a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

A semiconductor device may include a substrate, a stack of alternating gate and nanostructure layers above the substrate, and a first superlattice laterally adjacent the stack on a first side thereof and extending from the substrate to an upper surface of the stack to define a first source/drain region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The non-semiconductor monolayers of the first superlattice may be arranged along growth rings extending outwardly from respective adjacent nanostructure layer portions.

A semiconductor device includes a dielectric layer, a p-type transistor over a first side of the dielectric layer, and an n-type transistor over a second side of the dielectric layer opposite to the first side of the dielectric layer. The p-type transistor includes a semiconductor channel layer, a first gate structure over the semiconductor channel layer, and source/drain epitaxy structures on opposite sides of the first gate structure. The n-type transistor includes a semiconductive oxide channel layer, a second gate structure over the semiconductive oxide channel layer, and source/drain contacts on opposite sides of the second gate structure.

A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

Semiconductor device structures are provided. The semiconductor device structure includes a semiconductor substrate with an original semiconductor surface and an active region, a STI region surrounding the active region, a transistor formed based on the active region and including a gate structure, a first conductive region, a second conductive region and a channel region between the first and second conductive regions, an interconnection structure extending beyond the transistor, and a connecting plug electrically connecting the interconnection structure to the first conductive region of the transistor. The first conductive region includes an epitaxial semiconductor material. The interconnection structure is disposed under the original semiconductor surface and within the STI region.

Provided is a semiconductor device which includes: a 1.sup.st transistor including a 1.sup.st channel structure extended in a 1.sup.st direction, and a 1.sup.st gate structure on the 1.sup.st channel structure; a 2nd transistor comprising a 2.sup.nd channel structure extended in the 1.sup.st direction, and a 2.sup.nd gate structure on the 2.sup.nd channel structure, the 2.sup.nd transistor being disposed adjacent to the 1.sup.st transistor in a 2.sup.nd direction that horizontally intersects the 1.sup.st direction; a 1.sup.st isolation wall between the 1.sup.st channel structure and the 2.sup.nd channel structure; and a 1.sup.st gate cut structure between the 1.sup.st gate structure and the 2.sup.nd gate structure on the 1.sup.st isolation wall in a 3.sup.rd direction that vertically intersects the 1.sup.st direction and the 2.sup.nd direction.