Embodiments provided are a semiconductor device, including a first device. The first device includes a first protrusion protruding over a substrate; a first nanostructure including a first semiconductor material and disposed over the first protrusion; a first epitaxial extension region disposed on a first sidewall of the first nanostructure; a first gate structure including a first lower portion between the first nanostructure and the first protrusion; a first insulating spacer disposed on a second sidewall of the first lower portion of the first gate structure; and a first source/drain region disposed adjacent to the first protrusion and the first sidewall of the first nanostructure. The first source/drain region includes a first continuous semiconductor layer disposed on side surfaces of the first epitaxial extension region and the first insulating spacer. The first continuous semiconductor layer has a higher concentration of the second semiconductor material than the first epitaxial extension region.

Embodiments of the present disclosure provide a semiconductor device structure and methods for forming the same. The structure includes a first semiconductor layer disposed in a first region and a second semiconductor layer surrounding the first semiconductor layer in the first region. The first and second semiconductor layers comprise different materials. The structure further includes a first gate electrode layer surrounding a portion of the second semiconductor layer, a first source/drain region electrically connected to the second semiconductor layer, and a second source/drain region electrically connected to the second semiconductor layer. The second semiconductor layer is disposed between the first and second source/drain regions.

A semiconductor device includes a substrate, a source/drain region on the substrate, a channel structure on the substrate and electrically connected to the source/drain region, a gate structure on the substrate and at least partially surrounding the channel structure, and a stressor layer in contact with an upper surface of the source/drain region and configured to apply compressive stress or tensile stress to the source/drain region.

A device includes a substrate having a first side and a second side; a first transistor and a second transistor formed in a first level on the first side; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor formed in a second level on the first side; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side, the first and second interconnect structures each configured to carry a supply voltage, and the third and fourth interconnect structures each configured to carry a ground voltage; and a power structure vertically extending through the first and second levels, and configured to electrically couple a source/drain terminal of the third transistor and a source/drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively.

The method of manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, where in the thickness direction of the semiconductor substrate, the fin includes first sacrificial layers and channel layers alternately stacked and second sacrificial layers and a third sacrificial layer alternately stacked; forming a mask straddling the fin; selectively removing the second sacrificial layers to form a first dielectric filling region; forming first middle dielectric isolation layers in the first dielectric filling region; removing the first sacrificial layers, the channel layers, the first middle dielectric isolation layers, and the third sacrificial layer not covered by the mask; forming a first source region and a first drain region on both sides of the remaining first sacrificial layers and channel layer located below the remaining first middle dielectric isolation layers, respectively; and forming an insulating layer on the first source region and the first drain region.

An integrated circuit device includes a pair of stacked active-region structures extending in a first direction. The integrated circuit also includes a first switching gate-conductor, a first CFET gate-conductor, a second CFET gate-conductor, and a second switching gate-conductor intersecting the pair of stacked active-region structures and aligned correspondingly with a first gate track, a second gate track, a third gate track, and a fourth gate track extending in a second direction. A first CFET terminal-conductor extending in the second direction between the first gate track and the second gate track is conductively connected to the second CFET gate-conductor. A second CFET terminal-conductor extending in the second direction between the third gate track and the fourth gate track is conductively connected to the first CFET gate-conductor.

A memory device includes a substrate having a first side and a second side opposite to each other; a first transistor, a second transistor, and a third transistor formed at a first level on the first side of the substrate, the first to third transistors each formed with a first conductivity; and a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor formed at a second level on the first side of the substrate, the fourth to seventh transistors each formed with a second conductivity, wherein the first level is vertically disposed with respect to the second level. The first to seventh transistors operatively form a Static Random Access Memory (SRAM) cell.

A memory device includes a substrate having a first side and a second side; a first transistor, a second transistor, a third transistor, and a fourth transistor formed on the first side, the first to fourth transistors each formed with a p-type conductivity; a fifth transistor and a sixth transistor formed on the first side and over the first to fourth transistors, the fifth to sixth transistors each formed with an n-type conductivity; a first interconnect structure formed on the first side and over the fifth to sixth transistors, and coupled to the first transistor, wherein the first interconnect structure is configured as a portion of a first bit line; and a second interconnect structure formed on the second side, and also coupled to the first transistor, wherein the second interconnect structure is configured as another portion of the first bit line.

Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The structure includes a gate electrode layer disposed over a semiconductor layer, a source/drain region disposed adjacent the semiconductor layer, an interlayer dielectric (ILD) layer disposed over the source/drain region, a conductive feature disposed in the ILD layer over the source/drain region, a first dielectric layer disposed between the gate electrode layer and the conductive feature, a second dielectric layer distinct from the first dielectric layer disposed between the first dielectric layer and the gate electrode layer, a contact etch stop layer disposed between the second dielectric layer and the gate electrode layer, and a spacer disposed between the contact etch stop layer and the gate electrode layer.

Provided is a semiconductor device by which the integration level is improved, and specifically provided is a semiconductor device including a gate electrode extending lengthwise in a first direction, a plurality of channel layers that penetrate the gate electrode in a second direction intersecting the first direction, and are spaced apart in the first direction, and a gate insulating film including a plurality of gate insulating film patterns, each gate insulating film pattern at least partially covering a respective channel layer of the plurality of channel layers, wherein a height of each respective channel layer of the plurality of channel layers in a third direction intersecting with the first direction and the second direction is greater than a width of the respective channel layer of the plurality of channel layers in the first direction.