Embodiments of the present disclosure provide a semiconductor device including an air spacer between a source/drain contact and a gate structure and the method of forming the same. The formation of the air spacer includes forming an etch stop layer on an exposed source/drain surface, forming a sacrificial layer on the etch stop layer, depositing an isolation layer on the silicon layer, performing an anisotropic etching on the sacrificial layer while the etch stop layer protects the source/drain region to form the air spacer, and sealing the air spacer by implanting an interlayer dielectric layer above the gate structure.

Complementary Field-Effect Transistors (CFETs) are formed having different combinations of work function metal layers that produce different threshold voltages. A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming third nanostructures over a third region of the substrate; depositing a first gate electrode layer on the first nanostructures; depositing a second gate electrode layer on the second nanostructures and on the first gate electrode layer on the first nanostructures; depositing a third gate electrode layer on the third nanostructures, on the second gate electrode layer on the second nanostructures, and on the second gate electrode layer on the first nanostructures; and depositing a fourth gate electrode layer on the third gate electrode layer, on the first nanostructures, on the second nanostructures, and on the third nanostructures.

Provided is a semiconductor device which includes: a 1.sup.st source/drain region; a 2.sup.nd source/drain region above the 1.sup.st source/drain region; a side via structure connected to the 2.sup.nd source/drain region; a 1.sup.st backside contact plug on the 1.sup.st source/drain region; a 2.sup.nd backside contact plug on the side via structure; a 1st backside metal line on the 1.sup.st backside contact plug; a 2.sup.nd backside metal line on the 2.sup.nd backside contact plug; and a 1.sup.st deep trench isolation structure on a side surface of the 2.sup.nd backside contact plug.

Provided is a semiconductor device including a base pattern, channel layers disposed to be spaced apart from each other in a first direction perpendicular to a frontside of the base pattern on the frontside of the base pattern, a first source/drain area and a second source/drain area electrically connected to the channel layers on the frontside of the base pattern, a backside contact plug electrically connected to the first source/drain area from a backside of the base pattern, and a frontside contact plug electrically connected to the second source/drain area above the frontside of the base pattern, and the first source/drain area includes a first-first layer disposed on side surfaces of the channel layers of which each is perpendicular to a second direction crossing the first direction, and a first-second layer disposed on the first-first layer, and the backside contact plug is spaced apart from the first-first layer.

A source/drain (S/D) contact plug is formed in a complementary FET (CFET) device by: forming an S/D opening that extends through the upper S/D region, through a dielectric plug interposed between the upper and lower S/D regions, and into the lower S/D region, then filling the S/D opening with an electrically conductive material. The dielectric plug is surrounded by a contact etch stop layer (CESL). The CESL ensures that a pre-cleaning process for the S/D opening only removes dielectric material(s) disposed within an area defined by the CESL, thereby limiting the amount of widening in the S/D opening. This helps to prevent void (e.g., empty space) from being formed in the widened portion of the S/D opening, thus reducing the electrical resistance of the S/D contact plug, and preventing electrical short or leakage current between the S/D contact plug and an adjacent conductive feature.

An exemplary stacked device structure includes a semiconductor layer stack disposed over a substrate and a dual work function metal (DWFM) gate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The DWFM gate includes a first gate dielectric layer, a second gate dielectric layer, a first type work function metal layer, and a second type work function metal layer. The first gate dielectric layer is disposed over the first semiconductor layer, and the second gate dielectric layer is disposed over the second semiconductor layer. The first type work function metal layer is disposed over the first gate dielectric layer, and the second type work function metal layer is disposed over the second gate dielectric layer. At least one of the first type work function metal layer or the second type work function metal layer has a gradient composition.

A circuit device includes a substrate having an active region and an inactive region adjacent a periphery of the active region, lower channel structures respectively comprising one or more lower channel patterns stacked on the substrate in the active region and in the inactive region, isolation patterns on the lower channel structures opposite the substrate, and upper channel structures respectively comprising one or more upper channel patterns stacked on the isolation patterns opposite the lower channel structures. The one or more lower channel patterns in the inactive region are free of the one or more upper channel patterns thereon.

Embodiments of the present disclosure generally relate to metal gate devices. In one or more embodiments, a method for preparing a device with an airgap is provided and includes depositing a silicon-containing layer on inner surfaces of trenches formed in a metal-gate layer disposed on a substrate, depositing a carbon-containing layer on the silicon-containing layer in the trenches, the carbon-containing layer is deposited to fill at least a lower half of the trenches from the bottom, and leaving a temporary gap within each trench at the top. The method also includes depositing a low-k dielectric layer on the carbon-containing layer and the silicon-containing layer to fill the temporary gap, and exposing at least the carbon-containing layer to a treatment process to remove the carbon-containing layer and form the airgap between the silicon-containing layer and the low-k dielectric layer.

The present disclosure relates to a semiconductor device, and a semiconductor device according to an embodiment includes a substrate that includes a first well region having a first conductivity type and a second well region having a second conductivity type, a first lower pattern positioned in the first well region, a second lower pattern positioned in the second well region, a first channel pattern positioned on the first lower pattern, a second channel pattern positioned on the second lower pattern, a gate structure that surrounds the first channel pattern and the second channel pattern, a first source/drain pattern positioned on opposite sides of the first channel pattern, a first well tap pattern positioned on opposite sides of the second channel pattern, and a first barrier pattern positioned between the first source/drain pattern and the first lower pattern.

A three-dimensional transistor includes a first transistor structure including a first lower source/drain (S/D) region and a first upper S/D region contacting the first lower S/D region at a first junction region, where the first upper S/D region has a first conductivity type, and where the first lower S/D region has a second conductivity type that is opposite to the first conductivity type. The three-dimensional transistor includes a second transistor structure including a second lower S/D region and a second upper S/D region contacting the second lower S/D region at a second junction region, where the second upper S/D region has the first conductivity type, and where the second lower S/D region has the second conductivity type. The three-dimensional transistor includes a first collector/emitter contact electrically connecting the first upper S/D region and the second upper S/D region.