A semiconductor device includes a substrate including a logic cell region and an alignment mark region, a first active pattern on the substrate and in the logic cell region, the first active pattern extending in a first horizontal direction, a second active pattern on the substrate and in the logic cell region, the second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction that is different from the first horizontal direction, and a channel isolation layer on the substrate and in the logic cell region, the channel isolation layer extending in the first horizontal direction and isolating the first active pattern from the second active pattern in the second horizontal direction, where sidewalls of the channel isolation layer that are across the second horizontal direction contact the first active pattern and the second active pattern.

A method includes patterning a first opening through a first dielectric layer to expose a first source/drain region; forming a first silicide region on the first source/drain region; depositing a first plurality of polycyclic aromatic hydrocarbons along surfaces of the first opening; performing an annealing process to convert the first plurality of polycyclic aromatic hydrocarbons into a first graphene layer; and filling a remainder of the first opening with a first metal material. In another embodiment, the method further includes forming a second opening through the first dielectric layer, a second source/drain region, and a third dielectric layer to expose a third source/drain region, wherein in a top-down view the second source/drain region overlaps the third source/drain region.

A method includes forming a source/drain region, forming a contact etch stop layer over the source/drain region, forming an inter-layer dielectric over the contact etch stop layer, and performing an etching process to form a contact opening in the inter-layer dielectric and the contact etch stop layer. The source/drain region is exposed to the contact opening. A silicide formation process is performed to form a silicide region on a surface of the source/drain region. An etching process is performed to remove a metal that is deposited on dielectric regions, wherein the dielectric regions are exposed during the first silicide formation process. A contact plug is formed in the contact opening.

A three dimensional semiconductor device includes a bit line that is spaced apart from a substrate and extends in a direction perpendicular to a lower surface of the substrate, first semiconductor patterns on a first side surface of the bit line, the first semiconductor patterns including a first uppermost pattern which is an uppermost one of the first semiconductor patterns, and a word line surrounding the first semiconductor patterns. The first uppermost pattern includes a first top edge portion that is spaced apart from a second top edge portion in a first direction, and a first top channel region between the first top edge portion and the second top edge portion, a thickness of the first top edge portion is greater than a thickness of the first top channel region, and a thickness of the second top edge portion is greater than the thickness of the first top channel region.

A semiconductor structure includes an active region including a semiconductor fin base, a stack of nanostructures over the semiconductor fin base, and an epitaxial feature over the semiconductor fin base and connected to at least one of the nanostructures, the active region extending lengthwise in a first direction. The semiconductor structure further includes a gate structure wrapping around each of the nanostructures, the gate structure extending lengthwise in a second direction perpendicular to the first direction, and a backside butted contact disposed directly under and electrically connected to the epitaxial feature and the gate structure. A portion of the backside butted contact extends into the gate structure and the epitaxial feature.

A semiconductor device includes a substrate including a logic cell region and an ESD cell region, a plurality of active fins on the ESD cell region, disposed alternately in a first direction, including first active fins and second active fins disposed alternately and spaced apart in the first direction, a device isolation layer defining the first and second active fins, a pair of source/drain patterns on each of the plurality of active fins, spaced apart from each other in a second direction intersecting the first direction, a channel pattern between the pair of source/drain patterns, and a gate electrode extending in the first direction on the channel pattern, wherein each of the first and second active fins extending in the second direction, and a length of the first active fin in the second direction is greater than a length of the second active fin in the second direction.

Provided is an integrated circuit device including: first and second transistors including first and second channel regions and first and second source/drain regions respectively connected to the first and second channel regions; and first and second contact structures respectively connected to the first and second source/drain regions; wherein each of the first and second contact structures includes at least two metal-containing films, wherein the first contact structure includes a first major metal plug having a largest volume among volumes of the at least two metal-containing films of the first contact structure, wherein the second contact structure includes a second major metal plug having a largest volume among volumes of the at least two metal-containing films of the second contact structure, wherein the first and second major metal plugs respectively include different metals, and wherein the first and second major metal plugs have different cross-sectional shapes.

A semiconductor structure according to the present disclosure includes a backside metal line and a backside contact structure that includes a bar portion disposed on the backside metal line, a first via extending from the bar portion, a second via extending from the bar portion, and a protrusion disposed between the first via and the second via. The semiconductor structure also includes a first source/drain feature over the first via, a second source/drain feature over the second via, and a gate isolation feature disposed between the first via and the second via. The protrusion extends into the gate isolation feature.

Semiconductor structures and methods of fabricating the semiconductor structures are described. An exemplary method includes receiving an intermediate structure comprising an n-type transistor and a p-type transistor, forming a dielectric structure under the n-type transistor and the p-type transistor, forming a first trench and a second trench each extending through the dielectric structure, the first trench exposing a bottom surface of a source/drain feature of the n-type transistor, the second trench exposing a bottom surface of a source/drain feature of the p-type transistor, wherein a depth of the second trench is greater than a depth of the first trench, forming a first silicide layer and a second silicide layer in the first trench and the second trench, respectively, and forming a first backside via and a second backside via in the first trench and the second trench, respectively.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source/drain regions separated by channel regions. Gates at the channel regions formed fully around every surface of the channel region as gate-all-around (GAA) structures separated from channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes connected to the second source/drain regions and digit lines connected to the first source/drain regions.