A device including a base structure, and a superlattice structure, the superlattice structure disposed on the base structure. The superlattice structure includes a number of (IIIx, Aly)Oz layers, III being a Group 3 element different from Aluminum; where a composition (x, y) and thickness of each layer is selected to provide a preselected energy band structure.

A three-dimensional semiconductor device may include a first active region, which includes a first channel pattern and a first source/drain pattern connected to each other, on a substrate, a second active region, which includes a second channel pattern and a second source/drain pattern connected to each other, on the first active region, a gate electrode on the first and second channel patterns, a bottom active contact electrically connected to the first source/drain pattern and extended from the first source/drain pattern in a first direction, a lower metal layer provided below the bottom active contact, the lower metal layer including bottom via patterns and bottom interconnection lines electrically connected to the bottom active contact, and a division structure electrically connected to at least one of the bottom via patterns. The division structure may include a division liner pattern and a connection metal pattern penetrating the same.

A semiconductor device includes: an active region on a substrate; a gate structure intersecting the active region and including a gate electrode; a source/drain region on the active region; a first contact structure on and connected to the source/drain region; first and second insulating layers on the gate and first contact structures; a second contact structure connected to the gate electrode and including: a first contact via in the first insulating layer; and a first conductive cap layer in the second insulating layer and on the first contact via; a via structure connected to the first contact structure, the via structure including: a second contact via in the first insulating layer; and a second conductive cap layer in the second insulating layer and on the second contact via; and interconnection lines on the second insulating layer connected to the second contact structure and the via structure.

A semiconductor device may include a substrate including an active pattern, a lower power line in a lower portion of the substrate, a channel pattern on the active pattern and including a plurality of semiconductor patterns, which are stacked and include a first semiconductor pattern at the lowermost level, a gate electrode crossing the active pattern and including a first inner gate electrode between the active pattern and the first semiconductor pattern, source/drain patterns on the substrate, backside contacts connecting the lower power line to the source/drain patterns, and a filler structure between adjacent backside contacts among the backside contacts. The filler structure may include a filling pattern and a liner. The filling pattern may include a contact portion on a filler portion, and the liner may cover opposite side surfaces of the filler portion. The contact portion may be in direct contact with the substrate.

Forksheet field-effect transistor (FET) devices are provided. A forksheet FET device includes a first FET having a first conductive gate material. The forksheet FET device includes a second FET that is adjacent the first FET and that has the first conductive gate material. Moreover, the forksheet FET device includes a conductive wall that separates the first FET from the second FET. The conductive wall includes a second conductive gate material that is different from the first conductive gate material.

A semiconductor storage device including a two-port SRAM cell, in which nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

A semiconductor device includes: a substrate having first and second surfaces; a wordline including a front wiring pattern on the first surface and a back wiring pattern on the second surface; a bitline and a complementary bitline on the substrate; and first and second cells on the substrate. The first cell includes: a latch circuit with first and second inverters; a first pass transistor connected between an output node of the first inverter and the bitline; and a second pass transistor connected between an output node of the second inverter and the complementary bitline. The second cell includes a through via penetrating the substrate and connecting the front wiring pattern and the back wiring pattern.

A semiconductor device may include an active pattern on a substrate, first to third gate electrodes on the active pattern, a first source/drain region and a first source/drain contact between the first and second gate electrodes, a second source/drain region and a second source/drain contact between the second and third gate electrodes, a gate spacer on both sidewalls of the second gate electrode, a first interlayer insulating layer covering the first and second source/drain regions, and a second interlayer insulating layer in contact with at least a portion of sidewalls of the first source/drain contact. A lower surface of the second interlayer insulating layer may contact upper surfaces of the second gate electrode, the second source/drain contact, and the gate spacer between the second gate electrode and the second source/drain contact.

A semiconductor device includes an insulating base layer, a fin-type pattern on the insulating base layer and extending in a first direction, a plurality of channel structures on the fin-type pattern and spaced apart from each other in the first direction, each of the plurality of channel structures including a plurality of channel layers spaced apart from each other in a second direction that is perpendicular to the first direction, a plurality of gate structures respectively on the plurality of channel structures and extending in a third direction intersecting the first direction, source/drain patterns including a first source/drain pattern that is connected to side surfaces of some of the plurality of channel structures, internal spacers between the plurality of gate structures and the source/drain patterns, and a plurality of bottom isolation patterns respectively below the plurality of gate structures and between the insulating base layer and the fin-type pattern.

The present disclosure provides a semiconductor device, a method, and an electronic apparatus. The device includes: a substrate; a channel layer stacking portion including multiple channel layers along a thickness direction of the substrate, a length direction of the channel layer is perpendicular to the thickness direction of the substrate, and the channel layer includes a first end, a middle section and a second end along the length direction; a gate-all-around surrounding the middle section; a source/drain functional portion; and a spacer structure including first and second spacers. The first spacer is between first ends and second ends of adjacent channel layers, and includes a cavity. The second spacer is on a side of the channel layer stacking portion away from the substrate and on both sides of the gate-all-around along the length direction. A dielectric constant of the first spacer is greater than that of the second spacer.