Provided is a semiconductor device which includes: a 1.sup.st channel structure extended in a 1.sup.st direction; a 1.sup.st source/drain pattern on the 1.sup.st channel structure; a 2.sup.nd channel structure extended in the 1.sup.st direction at a side of the 1.sup.st channel structure in a 2.sup.nd direction intersecting the 1.sup.st direction; a 2.sup.nd source/drain pattern on the 2.sup.nd channel structure; and a 1.sup.st dielectric wall between the 1.sup.st channel structure and the 2.sup.nd channel structure, wherein the 1.sup.st source/drain pattern and the 2.sup.nd source/drain pattern are each of n-type, and a top surface and a side surface of each of the 1.sup.st channel structure and the 2.sup.nd channel structure is in a (110) orientation and in a (100) orientation, respectively.

An integrated circuit device includes an insulating structure, a first source/drain region on the insulating structure, a second source/drain region on the insulating structure and spaced apart from the first source/drain region, a gate structure including at least one gate electrode layer, the gate structure being between the first source/drain region and the second source/drain region, a contact plug connected to the gate structure, a first backside source/drain contact structure penetrating the insulating structure and connected to the first source/drain region, an electrical insulating layer on a side wall of an end portion of the first backside source/drain contact structure, the electrical insulating layer contacting the first source/drain region, and a first semiconductor material layer on the electrical insulating layer, where the electrical insulating layer is configured to electrically insulate the first semiconductor material layer from the first backside source/drain contact structure.

A semiconductor device may include an active pattern on a substrate, a first channel pattern and a second channel pattern provided on the active pattern and spaced apart from each other, a separation pattern between the first and second channel patterns, the separation pattern including a body portion and a head portion on the body portion, a gate electrode on the first and second channel patterns, and an inner insulating pattern on a side surface of the body portion. The inner insulating pattern may include a first portion between the first channel pattern and the separation pattern and between the second channel pattern and the separation pattern and a second portion between the gate electrode and the separation pattern. A width of the first portion may be larger than a width of the second portion.

An integrated circuit device includes a channel region, a gate line surrounding the channel region, a source/drain region contacting the channel region, and a backside via contact passing through a portion of the source/drain region in a vertical direction from a back side of the source/drain region. The source/drain region includes a bottom epitaxial layer protruding from a bottom surface of the source/drain region, a blocking epitaxial layer contacting the channel region and the bottom epitaxial layer, and a main epitaxial layer filling a space defined by the blocking epitaxial layer. A first dopant concentration of the bottom epitaxial layer is greater than a second dopant concentration of the blocking epitaxial layer and is greater than or equal to a third dopant concentration of the main epitaxial layer, and the backside via contact passes through at least a portion of the bottom epitaxial layer in the vertical direction.

The disclosed technology relates to dynamic random access memory (DRAM) devices. The disclosed technology provides an integrated DRAM device including a DRAM and a logic circuit configured to control the DRAM. In one aspect, a DRAM device includes a plurality of stacked transistors arranged in a first region of the DRAM device, the stacked transistors being disposed one over another along a stacking direction, and a storage capacitor arranged in a second region of the DRAM device. The first region is positioned above the second region along the stacking direction. One of the plurality of stacked transistors is connected to the storage capacitor to form a DRAM cell of the DRAM, and remaining one or ones of the plurality of stacked transistors forms at least a portion of the logic circuit.

A CFET transistor device, including: a substrate; a first semiconductor nanosheet and a second semiconductor nanosheet; an insulating layer arranged between the first and second nanosheets; a first gate arranged around a first part of the first nanosheet, and a second gate arranged around a first part of the second nanosheet; first inner spacers arranged against second parts of the first nanosheet, between which the first part of the first nanosheet is arranged, and second inner spacers arranged against second parts of the second nanosheet between which the first part is arranged; and wherein the first and second inner spacers respectively include first and second low-permittivity dielectric materials different from each other.

A semiconductor device includes a substrate, an active pattern on the substrate, a first channel pattern and a second channel pattern on the active pattern, a separation pattern between the first channel pattern and the second channel pattern, a gate electrode on the first channel pattern and the second channel pattern, and a gate insulating layer between the first channel pattern and the gate electrode and between the second channel pattern and the gate electrode, wherein the separation pattern includes a body portion and a head portion on the body portion, and the head portion includes an insulating pattern and an insulating layer on the insulating pattern.

A semiconductor device includes: a lower transistor including a lower channel structure and a lower source/drain structure on the lower channel structure; and an upper transistor above the lower transistor, the upper transistor including an upper channel structure and an upper source/drain structure on the upper channel structure, wherein a portion of the upper channel structure overlaps the lower channel structure in a vertical direction, and another portion of the upper channel structure does not overlap the lower channel structure in the vertical direction.

The present disclosure provides a method of manufacturing a stacked nanosheet gate-all-around field-effect transistor and a field-effect transistor. The method includes: forming a stack on a substrate, the stack includes multiple nanosheet layers and multiple silicon alloy layers alternately stacked; etching each silicon alloy layer to form a first cavity, the first cavity is between two adjacent nanosheet layers; manufacturing a protective layer in the first cavity, the protective layer covers an inner surface of the first cavity and is recessed to form a second cavity; manufacturing a gate electrode and two source/drain electrodes based on the second cavity, an air spacer is between the gate electrode and any source/drain electrode; and removing a first dielectric constant medium in a first space, the first space is in the air spacer and surrounded by an upper surface of the uppermost nanosheet layer, the gate electrode and any source/drain electrode.

A gate-all-around transistor, comprising: a semiconductor substrate, where a fin-shaped protrusion is provided at a surface of the semiconductor substrate on one side; a source and a drain arranged on the top surface of the fin-shaped protrusion, respectively; a gate comprising a first gate part on the top surface of the fin-shaped protrusion between the source and the drain and a second gate part on a surface of the first gate part on the side away from the fin-shaped protrusion; a first dielectric layer on two opposite sides of the first gate part in a first direction; a second dielectric layer on two opposite sides of the second gate part in the first direction; where: the first direction is parallel to the direction of connecting the source and the drain; a dielectric constant of the first dielectric layer is greater than that of the second dielectric layer.