A semiconductor device includes a lower interlayer insulating layer, a first plurality of bottom nanosheets, a first plurality of upper nanosheets, an upper isolation layer between the first plurality of bottom nanosheets and the first plurality of upper nanosheets, a first bottom gate electrode on the lower interlayer insulating layer, a first upper gate electrode on an upper surface of the first bottom gate electrode, and a first active cut that extends into each of the first bottom gate electrode and the first plurality of bottom nanosheets in the vertical direction and is on an upper surface of the lower interlayer insulating layer, where the first active cut is spaced apart from the first upper gate electrode in the vertical direction, and where the first active cut at least partially overlaps each of the first upper gate electrode and the first plurality of upper nanosheets in the vertical direction.

A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Embodiments described herein generally relate to methods of forming hardmask and bottom dielectric isolation layers in vertical trench structures. A method of forming a gate-all-around field-effect transistor includes depositing a conformal oxide layer on a channel surface and a bottom surface of vertical structures of a substrate, the vertical structures including an NMOS portion having NMOS vertical structures defining NMOS contact trenches and a PMOS portion having PMOS structures defining PMOS contact trenches having a PMOS source/drain layer deposited therein. The method further includes selectively etching the conformal oxide layer at the bottom surface of the vertical structures, inhibiting the conformal oxide layer, selectively depositing a nitride layer at the bottom surface of the vertical structures, etching the conformal oxide layer to expose the channel surface of the vertical structures, and depositing an NMOS source/drain layer on the bottom surface of the NMOS contact trenches.

A method of manufacturing a semiconductor device comprising: forming active structures; forming preliminary gate dielectric layers on the active structures; forming a first dipole layer including a first dipole material and a second dipole layer including a second dipole material on the preliminary gate dielectric layers; removing the first and second dipole layers in regions other than a first region of the active structures; removing a portion of the second dipole layer in regions other than a second region of the active structures, wherein each of the first and second regions includes at least two active structures, and the first region and the second region overlap to form an overlapping region; and performing a heat treatment process of diffusing the first and second dipole materials into the preliminary gate dielectric layers, wherein the overlapping region includes at least one of the active structures.

A semiconductor device may include a substrate insulating layer, a semiconductor pattern extending on the lower insulating pattern, a plurality of channel layers stacked on the semiconductor pattern, a gate structure surrounding the plurality of channel layers, a source/drain region on the semiconductor pattern and opposite sides of the gate structure, a backside contact structure including a contact region connected to the source/drain region, and an intermediate insulating pattern in contact with the semiconductor pattern. The backside contact structure may include a metal-semiconductor compound layer, a first insulating liner layer, a second insulating liner layer, and a conductive layer. The backside contact structure may pass through each of the substrate insulating layer, and the semiconductor pattern. The conductive layer may have a step portion between a first vertical region and a second vertical region of the backside contact structure.

An integrated circuit device includes a channel region, a gate line at least partially surrounding the channel region, the gate line having a first top surface extending in a first direction, wherein the first top surface of the gate line is a first distance apart from an uppermost surface of the channel region in a second direction perpendicular to the first direction, a source/drain region contacting the channel region, a source/drain contact located on the source/drain region and connected to the source/drain region, the source/drain contact having a second top surface coplanar with the first top surface of the gate line and extending in the first direction, and an etch stop insulating film extending from the first top surface of the gate line toward the second top surface of the source/drain contact in the first direction, the etch stop insulating film contacting the first top surface of the gate line.

A semiconductor device includes a transistor layer including a semiconductor substrate and gate structures on an upper surface of the semiconductor substrate, an upper substrate on the transistor layer, an upper wiring layer disposed between the transistor layer and the upper substrate and including upper conductive lines, a bonding layer between the upper wiring layer and the upper substrate, and a lower wiring layer disposed on a lower surface of the semiconductor substrate and including lower conductive lines. The transistor layer is disposed between the lower wiring layer and the upper wiring layer. The bonding layer includes a material having higher thermal conductivity than silicon oxide, and a dopant concentration of the upper substrate is lower than a dopant concentration of the semiconductor substrate.

The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.

An integrated circuit device includes: a first fin-type active region and a second fin-type active region that extend on a substrate in a straight line in a first horizontal direction and are adjacent to each other in the first horizontal direction; a fin isolation region arranged between the first fin-type active region and the second fin-type active region on the substrate and including a fin isolation insulation structure extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of gate lines extending on the first fin-type active region in the second horizontal direction, wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined to be closer to a center of the fin isolation region in the first horizontal direction from a lowermost surface to an uppermost surface of the first gate line.

A semiconductor device includes a lower interlayer insulating layer, an insulating pattern on an upper surface of the lower interlayer insulating layer, a plurality of bottom nanosheets on the insulating pattern, a nanosheet isolation layer on the plurality of bottom nanosheets, the nanosheet isolation layer including an insulating material, a plurality of upper nanosheets on an upper surface of the nanosheet isolation layer, a gate electrode on the insulating pattern, the gate electrode extending around each of the plurality of bottom nanosheets, the nanosheet isolation layer, and the plurality of upper nanosheets, a first bottom source/drain region on a first side of the gate electrode on the insulating pattern, and a first upper source/drain region on the first side of the gate electrode on the first bottom source/drain region, the first upper source/drain region spaced apart from the first bottom source/drain region.