A method includes forming a fin protruding from a substrate, where the fin includes semiconductor layers interleaved with dielectric sacrificial layers. The method includes forming inner spacers at end portions of each of the dielectric sacrificial layers. The method includes forming source/drain features in the fin adjacent to the inner spacers. The method includes removing a portion of the fin between adjacent source/drain features to form a trench. The method includes forming an isolation structure in the trench.

A semiconductor device includes a lower interlayer insulating layer and an active pattern thereon, wherein the active pattern extends in a first horizontal direction and is spaced apart from an upper surface of the lower interlayer insulating layer in a vertical direction; first nanosheets on the active pattern; second nanosheets spaced apart from the first nanosheets in the first horizontal direction on the active pattern; a first gate electrode extending in a second horizontal direction and extending around the first plurality of nanosheets; a capping layer on the first gate electrode; and an active cut on the lower interlayer insulating layer, wherein the active cut is spaced apart from the first gate electrode in the first horizontal direction, and an uppermost surface of the active cut is farther than an upper surface of the capping layer from the upper surface of the lower interlayer insulating layer.

A processing method includes forming an interfacial layer on a surface of a channel comprising silicon (Si) located between a source and a drain on a semiconductor substrate including a low- dielectric layer, and selectively depositing a high- dielectric layer directly on the interfacial layer relative to the low- dielectric layer by exposing the semiconductor substrate to a metal-containing precursor, a purge gas, an alcohol, and the purge gas.

An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure forming a high-k metal gate structure extending lengthwise along a first direction, forming a trench to separate the high-k metal gate structure into two portions, conformally depositing a first dielectric layer to substantially fill the trench, after the conformally depositing of the first dielectric layer, forming a patterned mask over the high-k metal gate structure, the patterned mask comprising an opening disposed directly over the trench, etching back the first dielectric layer while using the patterned mask as an etch mask to obtain a thinned first dielectric layer, and after the etching of the first dielectric layer, forming a second dielectric layer in the trench and on the thinned first dielectric layer.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source/drain regions separated by channel regions. Gates at the channel regions formed fully around every surface of the channel region as gate-all-around (GAA) structures separated from channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes connected to the second source/drain regions and digit lines connected to the first source/drain regions.

A semiconductor device may include an insulating pattern on a first lower interlayer insulating layer, nanosheets vertically stacked on the insulating pattern, a gate electrode on the insulating pattern and surrounding the nanosheets, a source/drain region on one side of the gate electrode on the insulating pattern, and a source/drain contact electrically connected to the source/drain region. The source/drain region, the first lower interlayer insulating layer, and the insulating pattern may define a contact trench and the source/drain contact may fill the contact trench. The source/drain contact may include a barrier layer, a first filling layer between parts of the barrier layer in the contact trench, and a second filling layer in the contact trench under the first filling layer. The first filling layer may be multi grain and may have a first average grain size. The second filling layer may be single grain.

A semiconductor device may include high-integrated memory cells, and a method for fabricating the semiconductor device may include forming a plurality of preliminary nano sheets disposed with first horizontal gaps therebetween over a substrate, forming a spacer layer surrounding portions of the preliminary nano sheets and defines second horizontal gaps between the preliminary nano sheets, forming gap-fill layers that fill the second horizontal gaps of the spacer layer, forming inter-cell dielectric layers on the gap-fill layers and the spacer layer, horizontally recessing the gap-fill layers and the spacer layer and forming a linear surrounding recess, and forming a conductive line horizontally extending while surrounding portions of the preliminary nano sheets in the linear surrounding recess.

A semiconductor device includes: a base pattern; a first metal structure penetrating the base pattern in a first direction; at least one gate structure including a gate electrode disposed on the first metal structure in the first direction; a second metal structure penetrating the base pattern in the first direction and spaced adjacent to the first metal structure in a second direction intersecting the first direction; and a source/drain structure including at least one of a source electrode or a drain electrode disposed on the second metal structure in the first direction, wherein the first metal structure and the second metal structure are electrically separated from each other by a blocking film.

A semiconductor device may include channels on a first region of a substrate, the channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and the substrate including the first region and a second region, a gate structure at least partially surrounding each of the channels, a bit line in contact with a first end portion of each of the channels, the bit line extending in the vertical direction, a first capacitor on a second end portion of each of the channels, semiconductor patterns arranged in the vertical direction on the second region of the substrate, each of the semiconductor patterns at least partially overlapping a respective one of the channels in a horizontal direction parallel to the upper surface of the substrate, and second capacitors on the semiconductor patterns, respectively.

A semiconductor device includes a first lower epitaxial pattern on a side of a gate structure, wherein the first lower epitaxial pattern is connected to a lower active pattern; a first upper epitaxial pattern on another side of the gate structure, wherein the first upper epitaxial pattern is connected to an upper active pattern; a cut pattern that is spaced apart from the lower and upper active patterns, is adjacent the gate structure, and extends in a first direction; and a via structure connected to the first lower epitaxial pattern and the first upper epitaxial pattern in the cut pattern, wherein the via structure includes a first pillar part overlapping the first upper epitaxial pattern in a second direction, a second pillar part overlapping the first lower epitaxial pattern in the second direction, and a connecting part extending in the first direction to connect the first and second pillar parts.