An etching composition including an alkaline compound (A) and a thiol compound (B), wherein the etching composition dissolves silicon.

Provided is a semiconductor device that includes a first active pattern and a second active pattern on a substrate, the first active pattern spaced apart from the second active pattern in a first direction, and extending in a second direction, the second direction being different from the first direction, a lower channel pattern and a lower source/drain pattern on the first active pattern and alternately arranged in the second direction, an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern, a gate pattern on first active pattern, the lower channel pattern, and the upper channel pattern, and a first active contact connected to the lower source/drain pattern, and a second active contact connected to the upper source/drain pattern.

A semiconductor device includes a lower interlayer insulating layer, an active pattern spaced, a plurality of nanosheets, a gate electrode, a source/drain region, a liner layer, a contact isolation layer, and a source/drain contact, where the sidewall of the contact isolation layer includes a first sidewall in contact with the source/drain contact in the first horizontal direction, a second sidewall in contact with each of the liner layer and the active pattern in the first horizontal direction, and a vertex between the first sidewall and the second sidewall, and where a slope profile of the first sidewall of the contact isolation layer and a slope profile of the second sidewall of the contact isolation layer are different.

A semiconductor structure includes: a substrate; and gate-all-around transistors on the substrate. Each gate-all-around transistor includes: a discrete protrusion on the substrate; a channel structure layer spaced apart from and suspended on the protrusion, including channel layers longitudinally stacked at intervals along a direction perpendicular to a surface of the substrate, a distance between the protrusion and a channel layer adjacent to the protrusion being larger than a distance between adjacent channel layers along the direction perpendicular to the surface of the substrate; a gate structure crossing the channel structure layer and surrounding each channel layer in the channel structure layer; a gate dielectric layer between the gate structure and the channel layers, and between the gate structure and the protrusion; and source-drain doped regions on the protrusion at two sides of the gate structure and in contact with ends of each channel layer along an extension direction.

Semiconductor devices having nanosheet architectures, e.g., transistors such as horizontal gate-all-around (hGAA) structures, methods, and apparatuses for forming such semiconductor devices are described. The methods comprise forming a cladding material around each of a first plurality of nanosheets; oxidizing a portion of the cladding material to form an oxidize film, such as a silicon oxide (SiO.sub.2) film, around the cladding material and a form a second plurality of nanosheets; annealing the second plurality of nanosheets at a temperature of less than or equal to 850 C.; and removing the oxide film.

Methods of forming and a semiconductor devices where the channel region includes a germanium-comprising layer; and a crystalline silicon layer on the germanium-comprising layer. A gate structure over a first surface and a second surface, the second surface opposing the first surface. In some implementations, the crystalline silicon layer can mitigate damage during processing.

Semiconductor structures and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.

Methods and devices are provided for enhanced contacts in vertical three-dimensional (3D) memory. Methods can include forming arrays of vertically stacked memory cells with horizontally oriented access devices and horizontally oriented storage nodes at each level of the vertical stack. Methods can include forming continuous, vertically oriented digit lines connected to the first source/drain regions of the horizontally oriented access devices, and forming contacts coupling the digit lines to logic components of the vertical three-dimensional (3D) memory. Forming the contacts can include forming a gettering material on upper surfaces of each digit line, and forming a conductive material on the gettering material.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

Provided is a semiconductor device including: a substrate; an active pattern on an upper side of the substrate; a gate structure on and intersecting the active pattern; a source/drain pattern on a side face of the gate structure and connected to the active pattern; an etch stop layer extending along an upper side of the substrate and an outer face of the source/drain pattern; a back side source/drain contact in the substrate, the back side source/drain contact being connected to the source/drain pattern; and a back side wiring structure on a lower side of the substrate and connected to the back side source/drain contact, wherein the back side source/drain contact extends along a part of a side face of the source/drain pattern, and wherein a part of the back side source/drain contact farthest from the lower side of the substrate is in contact with the etch stop layer.