A semiconductor device includes a first active pattern including first sheets spaced apart in a first direction perpendicular to a surface of a substrate, a second active pattern on the first active pattern and including second sheets spaced apart in the first direction, a first source/drain pattern connected to the first active pattern in a second direction, a second source/drain pattern on the first source/drain pattern and connected to the second active pattern in the second direction, and a gate electrode extending in a third direction and extending around the first and the second active patterns. The first source/drain pattern includes a first film along an inner surface of a recess where the first source/drain pattern is disposed and a second film on the first film and filling the recess. On a cross-section including the first and third directions, the recess decreases in width with decreasing distance to the substrate.

The present disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first direction. Each channel layer is encapsulated by a gate dielectric layer, and each first gate layer is arranged between two channel layers following another. The GAA transistor structure further comprises two second gate layers sandwiching the stack in a second direction and connected to the first gate layers. Each first gate layer is made of a first work function metal structure and each second gate layer is made of a second work function metal structure that is different from the first work function metal structure. Each first gate layer has a first thickness and each second gate layer has a second thickness larger than the first thickness.

An etching composition containing a semiclathrate hydrate-forming compound (A), wherein the compound (A) comprises a compound having a melting point of 5 C. or higher when the compound (A) is made into an aqueous solution having a concentration of 1 mol/L, the etching composition has an oxygen concentration of 2 ppm by mass or less, and the etching composition has a mass ratio of oxygen to the compound (A) of from 110.sup.8 to 110.sup.4.

A semiconductor device includes first source/drain patterns spaced apart in a first direction on a first region of a substrate, a first gate structure extending in a second direction intersecting the first direction, second source/drain patterns spaced apart in the first direction on a second region of the substrate, a second gate structure extending in the second direction, a first internal gate spacer between the first gate structure and one of the first source/drain patterns, and a second internal gate spacer between the second gate structure and one of the second source/drain patterns. The first and second internal gate spacers have first and second thicknesses, respectively, in the first direction. The first thickness of the first internal gate spacer at a center point thereof along the second direction is different from the second thickness of the second internal gate spacer at a center point thereof along the second direction.

A semiconductor device may include a substrate that comprises a first active pattern and a second active pattern that are spaced apart from each other; a first channel structure on the first active pattern; a first source/drain pattern on the first channel structure; a first pillar structure between the first active pattern and the second active pattern; and a second pillar structure on the first pillar structure, wherein the first pillar structure comprises a first upper surface that is in contact with the second pillar structure and a second upper surface that is higher than the first upper surface, wherein the first upper surface of the first pillar structure is lower than an uppermost surface of the first channel structure, wherein the second upper surface of the first pillar structure is lower than an upper surface of the second pillar structure.

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source/drain (S/D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S/D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S/D recesses by the nitride layers and form ILD recesses.

A semiconductor device includes a substrate insulating layer, a gate structure extending in a first direction on the substrate insulating layer, a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer, the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure, a first source/drain region and a second source/drain region, on both sides of the gate structure and connecting to the plurality of channel layers, a first spacer layer below the first source/drain region, and a second spacer layer below the second source/drain region, and a backside contact plug partially recessing a lower surface of the first source/drain region through the substrate insulating layer and the first spacer layer.

A semiconductor device includes a substrate insulating layer including an insulating pattern, a first gate structure and a second gate structure overlapping the insulating pattern, first semiconductor patterns spaced apart from each other and second semiconductor patterns spaced apart from each other, first and second source/drain regions respectively connected to the first and second semiconductor patterns, a first separation pattern extending between the first and second gate structures, the first separation pattern insulating the first and second gate structures from each other, a second separation pattern extending into respective at least portions of ones of the first semiconductor patterns and ones of the second semiconductor patterns, and a backside contact plug extending into the substrate insulating layer and connected to at least some of the source/drain regions. At least one of the first and second separation patterns includes an air gap.

Embodiments of the present disclosure provide a GAA device fabricated from a substrate having a (551)<110> top surface. Selecting the (551)/<110> substrate enables channel height scaling with improved hole mobility and without sacrificing electron mobility.

Methods of fabricating multigate transistors using dummy oxide interposers are disclosed herein. An exemplary method includes forming a multilayer stack that includes first semiconductor layers, sacrificial semiconductor layers, and a substrate extension. A source/drain recess is formed by removing the first semiconductor layers, sacrificial semiconductor layers, and a portion of the substrate extension in a source/drain region, and a source/drain structure is formed in the source/drain recess. The source/drain structure includes a second semiconductor layer and an insulator layer, and the insulator layer is disposed between the second semiconductor layer and the substrate extension. Before forming the source/drain structure, the sacrificial semiconductor layers are replaced with sacrificial dielectric layers. After forming the source/drain structure, the sacrificial dielectric layers are removed from a channel region to form a portion of a gate opening. A gate stack is formed in the portion of the gate opening.