An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

A method of manufacturing a semiconductor device includes forming a semiconductor device structure including a gate structure and source/drain regions disposed over a substrate, wherein the source/drain regions are embedded in the semiconductor device structure. An opening is formed in the semiconductor device structure over the source/drain region. A dopant is implanted into sidewalls of the opening. The opening is enlarged over the source/drain region. The source/drain region is exposed. A silicide layer is formed over the exposed source/drain region, and a conductive contact is formed in the opening.

A semiconductor device includes a substrate including an active region extending in a first direction, gate structures extending in a second direction overlapping the active region, on the substrate, and spaced apart from each other in the first direction, a blocking gate structure overlapping the active region, between the gate structures, and extending in the second direction, source/drain regions disposed in a region in which the active region is recessed, on both sides of the blocking gate structure, a backside contact structure disposed below at least one of the source/drain regions, and backside blocking structures disposed below the gate structures and the blocking gate structure, respectively. The blocking gate structure includes a first element different from the gate structures.

A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

Semiconductor devices according to some example embodiments include: a substrate; first channel patterns and second channel patterns that are spaced apart from each other on the substrate; an insulation structure between the first channel patterns and the second channel patterns; a gate structure that surrounds the first channel patterns, the second channel patterns, and at least a part of the insulation structure; and a source/drain pattern that is at both sides of each of the first channel patterns and the second channel patterns, wherein the insulation structure includes a first embedded insulation layer that is between the first channel patterns and the second channel patterns and extend in a first direction and a second embedded insulation layer between the first embedded insulation layer and the first channel patterns, and portions of the second embedded insulation layer are spaced apart from each other in the first direction.

Semiconductor devices and manufacture methods thereof are provided. In one aspect, a semiconductor device includes a first transistor, where the first transistor includes first channel patterns stacked on a first active pattern with a first channel length and first source and drain patterns; and a second transistor, where the second transistor includes second channel patterns stacked on a second active pattern with a second channel length greater than the first channel length and second source and drain patterns. Each of the first source and drain patterns include a first high-resistivity bottom epitaxial layer, a first epitaxial layer, and a second epitaxial layer. Each of the second source and drain patterns includes a third epitaxial layer on the second active pattern and a fourth epitaxial layer. A bottom level of the first source and drain patterns is lower than a bottom level of the second source and drain patterns.

There is provided a semiconductor device with improved yield and performance. The semiconductor device includes a substrate including a first region and a second region and having a first conductivity type, first and second active patterns spaced apart by a first pitch, on the first region, a first gate structure intersecting the first and second active patterns, first epitaxial patterns each having a second conductivity type, different from the first conductivity type, and receiving the same voltage level, on both sides of the first gate structure on each of the first and second active patterns, third and fourth active patterns spaced apart by a second pitch, on the second region, a second gate structure intersecting the third and fourth active patterns, and second epitaxial patterns each having the second conductivity type, on the sides of the second gate structure on each of the third and fourth active patterns, wherein the first pitch is n times the second pitch (where n is a natural number of 2 or greater), and no epitaxial pattern having the second conductivity type is disposed between the first and second active patterns

A semiconductor device includes a first region in which a passive element is provided, a second region adjacent to the first region and in which an active element is provided, a lower interlayer insulating layer in the first region and the second region, an insulating pattern in the second region and on an upper surface of the lower interlayer insulating layer, the insulating pattern extending in a first direction, a substrate in the first region, on the upper surface of the lower interlayer insulating layer, and spaced apart from the insulating pattern in the first direction, the substrate including silicon, and a field insulating layer in the second region and on the upper surface of the lower interlayer insulating layer, the field insulating layer at least partially surrounding a sidewall of the insulating pattern.

An integrated circuit device includes cell transistors at a first vertical level, a front wiring structure at a second vertical level higher than the first vertical level, and a rear wiring structure at a third vertical level lower than the first vertical level. The rear wiring structure includes a device isolation layer arranged on bottom surfaces of the cell transistors, rear contacts arranged in rear contact holes passing through the device isolation layer, a buried interconnector arranged in a recess region that extends into the device isolation layer, connected to a first and second rear contacts, among the rear contacts, and extending in a first horizontal direction or a second horizontal direction, a buried insulating layer arranged in the recess region and arranged on a bottom surface of the buried interconnector, and a rear wiring layer on bottom surfaces of the device isolation layer and the buried insulating layer.