A method produces a microelectronics device by hybrid bonding of individual chips onto a handle wafer, of the Die-to-Wafer type, includes a flow protocol for thinning the rear substrate of the chips. The flow protocol includes a pre-thinning grinding of the rear substrate of the individual chips once they have been attached to the wafer. This grinding is preceded by the formation of a protective layer protecting the trenches formed by the spaces between the attached individual chips. Next, a rectification etching rectifies the height of the rear substrate of each of the attached individual chips, via chemical wet etching, to eliminate the Total Thickness Variation. This etching is selective with respect to an etch-stop element contained in the respective substrates of the attached chips and which is used to stop the etching at a level that is substantially uniform for each of the chips.

An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

An electronic component includes a substrate having a first surface, a circuit board having a second surface facing the first surface, and an optical member having a third surface facing the first surface. The first surface of the substrate has a central region where a plurality of elements are arranged, the second surface of the circuit board is arranged above the first surface so as not to cover the central region, the third surface of the optical member is arranged above the central region without intervening the circuit board so as to have a space between the first surface and the third surface, and a plurality of microlenses are arranged on the third surface of the optical member.

An electronic component includes a substrate having a first surface, a circuit board having a second surface facing the first surface, and an optical member having a third surface facing the first surface. The first surface of the substrate has a central region where a plurality of elements are arranged, the second surface of the circuit board is arranged above the first surface so as not to cover the central region, the third surface of the optical member is arranged above the central region without intervening the circuit board so as to have a space between the first surface and the third surface, and a plurality of microlenses are arranged on the third surface of the optical member.

Provided is a glass circuit board and a manufacturing method thereof and an imaging device that achieve higher reliability. A glass circuit board including: a glass substrate serving as a core material including a first side, a second side located opposite from the first side, an outer end face located between the first side and the second side, and a through hole penetrating between the first side and the second side; an insulating first resin layer covering the first side; an insulating second resin layer covering the second side; a third resin layer that covers the inner surface of the through hole and is continuous with the first resin layer and the second resin layer; a fourth resin layer that covers the outer end face and is continuous with the first resin layer and the second resin layer; a first core wiring provided on the first side with the first resin layer interposed between the first core wiring and the first side; a second core wiring provided on the second side with the second resin layer interposed between the second core wiring and the second side; and a feed-through wiring provided on the inner surface of the through hole with the third resin layer interposed between the feed-through wiring and the inner surface.

A sensor package comprises a first substrate and a second substrate. A first substrate sensor element is mounted on an inner surface of the first substrate and between the first substrate and the second substrate, and a second substrate sensor element is mounted on an inner surface of the second substrate and between the first substrate and the second substrate. A first side sensor element and a second side sensor element are mounted vertically between the first substrate and the second substrate, wherein the first and second side sensor elements have respective sensing areas facing away from each other and outwards of the sensor package, and wherein the first and second side sensor elements are electrically coupled to at least one of the first substrate and the second substrate. A first side clear mold and a second side clear mold are formed to cover the respective sensing areas of the first and second side sensor elements. An encapsulant layer is formed between the first substrate and the second substrate to encapsulate the first substrate sensor element, the second substrate sensor element and the first and second side sensor elements.

A sensor package comprises a first substrate and a second substrate. A first substrate sensor element is mounted on an inner surface of the first substrate and between the first substrate and the second substrate, and a second substrate sensor element is mounted on an inner surface of the second substrate and between the first substrate and the second substrate. A first side sensor element and a second side sensor element are mounted vertically between the first substrate and the second substrate, wherein the first and second side sensor elements have respective sensing areas facing away from each other and outwards of the sensor package, and wherein the first and second side sensor elements are electrically coupled to at least one of the first substrate and the second substrate. A first side clear mold and a second side clear mold are formed to cover the respective sensing areas of the first and second side sensor elements. An encapsulant layer is formed between the first substrate and the second substrate to encapsulate the first substrate sensor element, the second substrate sensor element and the first and second side sensor elements.

The disclosed semiconductor device package may include a compute chip configured to perform contextual artificial intelligence and machine perception operations. The disclosed semiconductor device package may additionally include a sensor positioned above the compute chip in the semiconductor device package. The disclosed semiconductor device package may also include one or more electrical connections configured to facilitate communication between the compute chip and the sensor, between the compute chip and a printed circuit board, and between the sensor and the printed circuit board. Various other methods, systems, and computer-readable media are also disclosed.

The disclosed semiconductor device package may include a compute chip configured to perform contextual artificial intelligence and machine perception operations. The disclosed semiconductor device package may additionally include a sensor positioned above the compute chip in the semiconductor device package. The disclosed semiconductor device package may also include one or more electrical connections configured to facilitate communication between the compute chip and the sensor, between the compute chip and a printed circuit board, and between the sensor and the printed circuit board. Various other methods, systems, and computer-readable media are also disclosed.