Provided is a vision sensor comprising a first semiconductor die comprising a plurality of photoelectric conversion element groups, and a second semiconductor die comprising a dynamic vision sensor (DVS) pixel circuit and stacked on the first semiconductor die in a copper-to-copper bonding manner, wherein each of the plurality of photoelectric conversion element groups comprises, a first-type photoelectric conversion element configured to output an electrical signal corresponding to an amount of light incident on the first-type photoelectric conversion element, and a plurality of the second-type photoelectric conversion elements, wherein each second-type photoelectric conversion elements is configured to output charges corresponding to an amount of light incident on the second-type photoelectric conversion element, wherein the DVS pixel circuit is configured to output an event signal based on the charges generated by the plurality of second-type photoelectric conversion elements, and wherein, in each the plurality of photoelectric conversion element groups, a total number of second-type photoelectric conversion elements is greater than a total number of first-type photoelectric conversion elements.

Provided is a vision sensor comprising a first semiconductor die comprising a plurality of photoelectric conversion element groups, and a second semiconductor die comprising a dynamic vision sensor (DVS) pixel circuit and stacked on the first semiconductor die in a copper-to-copper bonding manner, wherein each of the plurality of photoelectric conversion element groups comprises, a first-type photoelectric conversion element configured to output an electrical signal corresponding to an amount of light incident on the first-type photoelectric conversion element, and a plurality of the second-type photoelectric conversion elements, wherein each second-type photoelectric conversion elements is configured to output charges corresponding to an amount of light incident on the second-type photoelectric conversion element, wherein the DVS pixel circuit is configured to output an event signal based on the charges generated by the plurality of second-type photoelectric conversion elements, and wherein, in each the plurality of photoelectric conversion element groups, a total number of second-type photoelectric conversion elements is greater than a total number of first-type photoelectric conversion elements.

An apparatus includes a multi-spectral sensor and an image sensor. The multi-spectral sensor includes a spectrometer having at least a first optical filter and a second optical filter. The first optical filter includes a first lattice of nanowires having a first geometric property and configured to detect light within a first spectral band. The second optical filter includes a second lattice of nanowires having a second geometric property and configured to detect light within a second spectral band. The first spectral band and the second spectral band can at least partially define a spectral resolution of the spectrometer. The image sensor includes a first pixel configured to generate a first signal in response to receiving the light within the first spectral band, and a second pixel configured to generate a second signal in response to receiving the light within the second spectral band.

An apparatus includes a multi-spectral sensor and an image sensor. The multi-spectral sensor includes a spectrometer having at least a first optical filter and a second optical filter. The first optical filter includes a first lattice of nanowires having a first geometric property and configured to detect light within a first spectral band. The second optical filter includes a second lattice of nanowires having a second geometric property and configured to detect light within a second spectral band. The first spectral band and the second spectral band can at least partially define a spectral resolution of the spectrometer. The image sensor includes a first pixel configured to generate a first signal in response to receiving the light within the first spectral band, and a second pixel configured to generate a second signal in response to receiving the light within the second spectral band.

A semiconductor package including a package substrate; an intermediate substrate on the package substrate; an optical engine unit on the intermediate substrate; a logic device adjacent to the optical engine unit and on the intermediate substrate; and a memory device adjacent to the logic device and on the intermediate substrate, wherein the optical engine unit includes a first redistribution substrate, a photonic integrated circuit (PIC) chip on the first redistribution substrate, an electronic integrated circuit (EIC) chip on the PIC chip, a multi-insulating layer surrounding the PIC chip and the EIC chip, and a transparent support layer on the EIC chip and the multi-insulating layer.

A semiconductor package includes a first chip structure on a first substrate and a first molding layer surrounding the first chip structure on the first substrate, wherein the first chip structure includes a first chip including a PIC on the first substrate, a second chip including an EIC on the first chip, a transparent layer horizontally spaced from the second chip on the first chip, a microlens layer on the transparent layer; and a second molding layer surrounding the second chip, the transparent layer, and the microlens layer on the first chip, the semiconductor package further includes a first insulating layer on an upper surface of the first chip and a second insulating layer on a lower surface of the transparent layer, and the first and second 10 insulating layers are in contact with each other, and the first and second insulating layers are integrally formed of the same material.

A semiconductor package includes a first chip structure on a first substrate and a first molding layer surrounding the first chip structure on the first substrate, wherein the first chip structure includes a first chip including a PIC on the first substrate, a second chip including an EIC on the first chip, a transparent layer horizontally spaced from the second chip on the first chip, a microlens layer on the transparent layer; and a second molding layer surrounding the second chip, the transparent layer, and the microlens layer on the first chip, the semiconductor package further includes a first insulating layer on an upper surface of the first chip and a second insulating layer on a lower surface of the transparent layer, and the first and second 10 insulating layers are in contact with each other, and the first and second insulating layers are integrally formed of the same material.

A chip structure includes a photonic integrated circuit chip including a waveguide extending in a horizontal direction, an electronic integrated circuit chip on the photonic integrated circuit chip, a silicon block above the photonic integrated circuit chip in a vertical direction and spaced from the electronic integrated circuit chip in the horizontal direction, a first insulating layer at least partially surrounding the electronic integrated circuit chip and the silicon block, and a silicon support on an upper surface of the electronic integrated circuit chip, an upper surface of the silicon block, and an upper surface of the first insulating layer, where the silicon support includes a micro lens, the micro lens is below an upper surface of the silicon support, and the silicon block includes a material that is the same as a material of the silicon support.

Provided is a semiconductor package including a substrate, a first chip on the substrate and including a photonic integrated circuit (PIC), a second chip on the first chip and including an electronic integrated circuit (EIC), a support block spaced apart from the second chip and bonded to an upper surface of the first chip, a molding layer on the first chip and at least partially surrounding the second chip and the support block, with an upper surface of the support block free of the molding layer, a micro-lens layer on the molding layer, the first chip, and the support block, and a first transparent adhesive layer between a lower surface of the micro-lens layer and an upper surface of the molding layer, and between the lower surface of the micro-lens layer and the upper surface of the support block.

Provided is a semiconductor package including a substrate, a first chip on the substrate and including a photonic integrated circuit (PIC), a second chip on the first chip and including an electronic integrated circuit (EIC), a support block spaced apart from the second chip and bonded to an upper surface of the first chip, a molding layer on the first chip and at least partially surrounding the second chip and the support block, with an upper surface of the support block free of the molding layer, a micro-lens layer on the molding layer, the first chip, and the support block, and a first transparent adhesive layer between a lower surface of the micro-lens layer and an upper surface of the molding layer, and between the lower surface of the micro-lens layer and the upper surface of the support block.