Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

The present disclosure describes a semiconductor device having a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapped around the central portion of the channel structure, a source/drain (S/D) structure on the substrate and adjacent to the end portion of the channel structure, and an extension structure between the channel structure and the S/D structure. The extension structure has a first sidewall having a first height and adjacent to the end portion of the channel structure and a second sidewall having a second height and adjacent to the S/D structure greater than the first height.

An integrated circuit device includes a first gate line and a second gate line adjacent to each other in a first horizontal direction and extending in a second horizontal direction that is perpendicular to the first horizontal direction, a source/drain region between the first gate line and the second gate line, a backside via contact connected to the source/drain region, and a first backside bulk insulating film and a second backside bulk insulating film, where, in the first horizontal direction, the backside via contact is between the first backside bulk insulating film and the second backside bulk insulating film, where each of the first backside bulk insulating film and the second backside bulk insulating film includes a vertical insulating portion below one gate line among the first gate line and the second gate line in a vertical direction and extending in the vertical direction.

A semiconductor device includes: a substrate; source/drain patterns on the substrate; a channel pattern between the source/drain patterns, the channel pattern including a plurality of semiconductor patterns; a gate electrode between the plurality of semiconductor patterns; an upper separation structure extending in a first direction and spaced apart from the gate electrode in a second direction intersecting the first direction; a first backside separation structure penetrating the substrate below the gate electrode in a third direction intersecting the first direction and the second direction; and a second backside separation structure penetrating the substrate and overlapping the upper separation structure in the third direction.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternatingly stacked first semiconductor layers and second semiconductor layers. The method also includes laterally recessing the first semiconductor layers of the fin structure to form a plurality of notches, forming a plurality of inner spacers in the notches, laterally recessing the inner spacers to form a plurality of recesses in the inner spacers, and growing a source/drain feature over the fin structure. The recesses are sealed by the source/drain feature and the inner spacers to form a plurality of air spacers.

The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shape structure, forming a dummy gate stack over a channel region of the fin-shape structure, recessing a source/drain region to form a source/drain trench, forming an epitaxial feature in the source/drain trench, after the forming of the epitaxial feature removing the dummy gate stack, releasing the channel layers in the channel region as channel members, forming a gate structure wrapping around each of the channel members, and after the forming of the gate structure performing an ion implantation to increase a dopant concentration of a dopant in the epitaxial feature.

A method of manufacturing a semiconductor device includes forming an interfacial layer over a channel region and forming a metal-containing layer over the interfacial layer. A metal silicate layer is formed over the channel region after forming the metal-containing layer. A portion of the metal silicate layer is removed. A gate dielectric layer is formed over the channel region after removing the portion of the metal silicate layer, and a gate electrode layer is formed over the gate dielectric layer.

The semiconductor device includes active patterns on a substrate, each of the active patterns extending in a first direction, and an isolation pattern is on at least a portion of respective sidewalls of each of the active patterns, a gate structure on the active patterns and on the isolation pattern, the gate structure extending in a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction, a mask pattern on the gate structure, a sidewall of the mask pattern is aligned with a sidewall of the gate structure, and a division pattern on the isolation pattern, the division pattern in contact with the sidewall of the gate structure and the sidewall of the mask pattern.

A semiconductor structure is provided. The semiconductor structure includes a first set of nanostructures that are stacked vertically and spaced apart from one another and formed in a first well, a source/drain feature adjoining the first set of nanostructures, a first top gate electrode layer above a topmost nanostructure in the first set of nanostructures, and an inner gate electrode layer sandwiched between the nanostructures. A first dimension of the inner gate electrode layer in a first direction is greater than a second dimension of the first top gate electrode layer in the first direction.

Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.