Proposed are a precursor for forming a scandium- or yttrium-containing thin film, the precursor being characterized by including a compound represented by Chemical Formula 1, a method for forming a scandium- or yttrium-containing thin film using the same, and a semiconductor device including the scandium- or yttrium-containing thin film. The precursor for forming the thin film contains an amidinate ligand and thus can exhibit chemical characteristics such as low viscosity, high heat resistance, and high volatility, thereby enabling the formation of a high-quality thin film.

A semiconductor device such as a capacitor or transistor has an interface layer comprising a metallic transition metal dichalcogenide material. The interface layer may be formed adjacent to the dielectric layer and may include a monolayer, a bilayer, or more layers of one or more metallic transition metal dichalcogenides. The interface layer is incorporated in a capacitor stack and is preferably deposited using atomic layer deposition.

A method of manufacturing a semiconductor device includes: forming a lower electrode on a substrate; forming, on the lower electrode, a high dielectric constant film made of an oxide containing a tetravalent metal cation; forming, on the high dielectric constant film, an oxide film made of an oxide containing a pentavalent metal cation; forming a mixed layer having conductivity, in which the oxide containing the tetravalent metal cation and the oxide containing the pentavalent metal cation are mixed, by causing the high dielectric constant film to react with the oxide film; and forming an upper electrode.

The disclosed and claimed subject matter relates to (1) a process for performing thermal atomic layer etching (ALE) of films that include ZrO.sub.2, HfO.sub.2, (HfZr)O.sub.2 alloy or similar materials which does not require the use of plasmas or corrosive halogenating chemistries and (2) a metal-insulator-metal capacitor (MIMcap) with unique properties enabled by a unique dielectric processing method.

A capacitor includes a first electrode layer, a second electrode layer; and a strontium titanate dielectric layer formed between the first electrode layer and the second electrode layer, where in a direction from the center of the strontium titanate dielectric layer to two opposite sides of the strontium titanate dielectric layer, ratios of Sr/(Sr+Ti) in the strontium titanate dielectric layer decrease gradually, one side of the two opposite sides in the strontium titanate dielectric layer is close to the first electrode layer, and the other side of the two opposite sides in the strontium titanate dielectric layer is close to the second electrode layer.

The present disclosure relates to memories, electronic devices, and memory manufacturing methods. One example memory includes a memory array chip and a control circuit chip. The memory array chip includes a first substrate and a plurality of memory cells formed on the first substrate, and each memory cell includes a transistor and at least one capacitor electrically connected to the transistor. The control circuit chip includes a second substrate and a circuit structure formed on the second substrate, and the circuit structure is configured to control reading/writing of the plurality of memory cells. The plurality of memory cells and the circuit structure face each other and are electrically connected to each other through a bonding structure formed between the circuit structure and the plurality of memory cells.

An integrated electrical device that includes an energy storage component, the component having, above a support, a bottom electrode layer, an intermediate layer having a dielectric layer or an ionic conductor layer above the bottom electrode layer, and a top electrode layer above and on the intermediate layer, wherein the intermediate layer is in contact with the bottom electrode layer and with the top electrode layer in a central region, and the intermediate layer is are spaced apart from either the bottom electrode layer or the top electrode layer by a buffer layer in a peripheral region that surrounds the central region, the buffer layer including an insulating material and arranged on the bottom electrode layer or on the intermediate layer, the buffer layer having an opening that opens onto the bottom electrode layer or onto the intermediate layer so as to define the central region.

A semiconductor device includes a main conductive region, a first conductive region, a second conductive region, a first first-side dielectric layer (first inner dielectric layer), a second first-side dielectric layer (second inner dielectric layer), a first second-side dielectric layer (first outer dielectric layer), and a second second-side dielectric layer (second outer dielectric layer). A main trench extends from the surface of an epitaxial semiconductor layer to penetrate a base epitaxial semiconductor layer and the main conductive region is electrically connected to a semiconductor substrate. A first trench and a second trench respectively extend from the surface of the epitaxial semiconductor layer to reach the base epitaxial semiconductor layer, and the first conductive region and the second conductive region are electrically insulated from the base epitaxial semiconductor layer.

Disclosed are a device and method for an electronic device including a capacitor. The capacitor may include a first electrode; a second electrode disposed spaced apart from the first electrode; and a dielectric layer disposed between the first electrode and the second electrode, wherein the dielectric layer comprises: a first hafnium zirconium oxide layer region disposed in contact with or adjacent to the first electrode, and being doped with a first doping material, and a second hafnium zirconium oxide layer region disposed in contact with or adjacent to the second electrode, and being doped with a second doping material different from the first doping material; and an interlayer region disposed between the first and second hafnium zirconium oxide layer regions.

A method of fabricating a capacitor includes forming a lower electrode on a semiconductor substrate in a reaction space. A homogeneous oxide layer is formed on the lower electrode. A dielectric layer is formed on the homogeneous oxide layer. An upper electrode is formed on the dielectric layer. The forming of the homogeneous oxide layer includes performing a homogeneous oxide layer forming cycle at least one time. The homogeneous oxide layer forming cycle includes supplying an oxidizing agent, purging the oxidizing agent, and pumping-out the reaction space.