Provided is a method of manufacturing a semiconductor device, the method including forming a first mold structure and a second mold structure on a semiconductor structure, the second mold structure being spaced apart from the first mold structure in a horizontal direction, the first mold structure including first insulating films and second insulating films different from the first insulating films alternately stacked one-by-one, and the second mold structure including a third insulating film including a material same as a material of each of the first insulating films, forming a mask pattern on the first mold structure and the second mold structure, and etching, using a first etching gas, the first mold structure and the second mold structure based on the mask pattern, wherein the first etching gas includes oxygen-containing fluorocarbon.

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

According to at least one embodiment of the present disclosure, there is provided a capacitor structure including a lower electrode including a first lower electrode and a second lower electrode, an upper electrode, a supporter in contact with the first lower electrode and the second lower electrode, a dielectric layer between the lower electrode and the upper electrode, a lower interface layer between the lower electrode and the dielectric layer, the lower interface layer including a first material that is a conductive material and includes nitrogen (N), and a supporter interface layer between the supporter and the dielectric layer, and the supporter interface layer including a second material, the second material being an insulator and including nitrogen (N).

The present invention provides a semiconductor device and a method of fabricating the same, which includes: providing a semiconductor substrate having a first patterned region and a second patterned region and performing floating-gate poly-Si deposition on the semiconductor substrate thereby forming a first poly-Si layer, wherein the first patterned region has a higher feature density than the second patterned region; performing ion implantation on the first poly-Si layer and forming an oxide layer over a top surface of the first poly-Si layer; with the oxide layer in the second patterned region being protected, etching the oxide layer in the first patterned region; performing a CMP process on the first poly-Si layer in the first patterned region and on the oxide layer and the first poly-Si layer in the second patterned region; and forming the semiconductor device on the basis of the first poly-Si layer that has undergone the CMP process.

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

A ferroelectric memory device and a method for manufacturing the ferroelectric memory device are provided. The ferroelectric memory device includes a substrate, and capacitors stacked on the substrate. Each of the capacitors includes a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, and the first electrode includes a flat portion and an upper protrusion on the flat portion. The flat portion has a first width in a first direction parallel to an upper surface of the substrate, and the upper protrusion has a second width smaller than the first width in the first direction.

A process for depositing a metal-niobium oxide film on a substrate using a deposition method may include a plurality of complete deposition cycles. Each complete deposition cycle may comprise performing a metal-oxidizer sub-cycle followed by a niobium sub-cycle. The metal-oxidizer sub-cycle may comprise contacting the substrate with a metal precursor and a first oxygen precursor. The niobium sub-cycle may comprise contacting the substrate with at least a niobium precursor.

A semiconductor device that includes a substrate having an insulating surface; a first electrode on the insulating surface; a dielectric film on the first electrode; and a second electrode on the dielectric film. The second electrode has a protruding shape in a sectional view.

A nitride semiconductor device is a nitride semiconductor device including an active element and a passive element, and includes: a nitride semiconductor layer divided into an active region and an inactive region in a plan view; and a metal layer in contact with the nitride semiconductor layer in the inactive region. The active element is provided in the active region, and the passive element is provided in the inactive region. The metal layer includes a coherent state or a metamorphic state relative to the nitride semiconductor layer.

Disclosed a semiconductor structure includes: a substrate, including a device layer, a buried power rail, and a through silicon via, where the through silicon via is connected to the device layer through the buried power rail; a power network layer, disposed on the substrate, where the power network layer includes at least one layer of a first power array and at least one layer of a second power array, and each of the at least one layer of the first power array is connected to the buried power rail through the through silicon via; and a capacitor structure, disposed between each of the at least one layer of the first power array and each of the at least one layer of the second power array and connected to the first power array and the second power array through a lower electrode and an upper electrode of the capacitor structure respectively.