Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

A method for manufacturing a semiconductor device includes: forming a two-dimensional material layer made of transition metal dichalcogenides on a semiconductor substrate unit; forming two lower metallic layers made of first metallic material and spaced apart on the two-dimensional material layer; forming two upper metallic layers made of second metallic material respectively on the two lower metallic layers so as to form two double-layer metal structures; and subjecting the two double-layer metal structures to a selective annealing process and cooling to room temperature. The semiconductor device made by the method is also provided.

A halide perovskite-based complementary semiconductor device according to an embodiment of the present invention includes a substrate, a two-dimensional material layer formed on an upper surface side of the substrate and including a hole injection layer and an electron injection layer, a halide perovskite layer formed on the two-dimensional material layer, and an electrode layer formed on the halide perovskite layer and including a drain electrode, an output electrode, and a source electrode.

A semiconductor device and a method of fabricating the same are provided. The semiconductor device may include a source electrode, a drain electrode, an insulating region between the source electrode and the drain electrode, and a channel layer. The channel layer may be on the source electrode, the insulating region, and the drain electrode. The channel layer may include a source region on the source electrode, a drain region on the drain electrode, and a channel region on the insulating region. The source region and the drain region may include a precious metal element. The precious metal element in the drain region may be the same as the precious metal element in the source region. The channel region may include a first two-dimensional material layer having precious metal element-based semiconductor characteristics that may be the same as precious metal element-based semiconductor characteristics of the precious metal element.

A semiconductor device may include a first gate electrode and a second gate electrode spaced apart from each other on a substrate, a first channel layer on one side of the first gate electrode, a second channel layer on one side of the second gate electrode, and a third gate electrode connecting the first gate electrode and the second gate electrode to each other. The first channel layer and the second channel layer may extend in a first direction and the first direction may be perpendicular to the substrate.

Provided are semiconductor devices and methods of fabricating the semiconductor device. The semiconductor device includes a channel, a first source/drain and a second source/drain being apart from each other in a first direction with the channel therebetween, a gate electrode surrounding the channel, an alternating-current wiring line configured to provide alternating current to the channel, and a first conductive contact connecting the alternating-current wiring line and the first source/drain to each other. A height difference from a first surface of the gate electrode facing the alternating-current wiring line to a first surface of the first source/drain in contact with the first conductive contact is less a height difference from a second surface of the gate electrode opposing the first surface of the gate electrode to a second surface of the first source/drain opposing the first surface of the first source/drain.

The present invention relates to the field of semiconductor devices, specifically addressing challenges in interconnectivity and transistor density. This patent describes a novel method utilizing 2D semiconductors for the creation of monolithic 3D integrated multi-tier circuits on top of an integrated circuit. The invention achieves substantially higher vertical interconnect bandwidth, significantly increased IO density, and orders of magnitude lower signal transmission delay compared to conventional methods like through-silicon via (TSV) or copper-to-copper hybrid bonding. These advancements are made possible by stacking integrated circuit layers monolithically, connecting layers with vias, and utilizing 2D semiconductor-based transistors. Furthermore, the invention allows for a substantial increase in transistor density, contributing to enhanced processing capability. The utilization of more cost-effective process nodes further enhances the economic viability of the invention.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A two-dimensional (2D) material growth substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a strain control buffer layer formed on the second surface of the semiconductor substrate; a surface protective layer formed on the first surface of the semiconductor substrate; and a 2D material layer formed on the surface protective layer. The 2D material layer is configured to generate one of a tensile strain and a compressive strain. The semiconductor substrate and the strain control buffer layer include materials having different thermal expansion coefficients, and a combined thermal expansion coefficient of the semiconductor substrate and the strain control buffer layer is substantially similar to a thermal expansion coefficient of the 2D material layer.

Provided is a semiconductor device by which the integration level is improved, and specifically provided is a semiconductor device including a gate electrode extending lengthwise in a first direction, a plurality of channel layers that penetrate the gate electrode in a second direction intersecting the first direction, and are spaced apart in the first direction, and a gate insulating film including a plurality of gate insulating film patterns, each gate insulating film pattern at least partially covering a respective channel layer of the plurality of channel layers, wherein a height of each respective channel layer of the plurality of channel layers in a third direction intersecting with the first direction and the second direction is greater than a width of the respective channel layer of the plurality of channel layers in the first direction.