Disclosed herein are a field effect transistor and a preparation method therefor, and a memory and a display. The field effect transistor comprises: a first source/drain layer (1), an insulating layer (2) and a second source/drain layer (3), which are sequentially stacked; and a gate electrode (5) and a channel layer (4), which surrounds the gate electrode (5), wherein the gate electrode (5) and the channel layer (4) are located in the second source/drain layer (3) and the insulating layer (2), and the channel layer (4) is in contact with the first source/drain layer (1) and the second source/drain layer (3). The channel layer (4) comprises an outer layer and an inner layer (42), wherein the inner layer (42) is close to the gate electrode (5); the outer layer is in contact with the insulating layer (2), the first source/drain layer (1) and the second source/drain layer (3); and both the outer layer and the inner layer (42) are made of indium oxide. Since both the outer layer and the inner layer (42) of the channel layer (4) in the field effect transistor are made of indium oxide, the problems of further reducing the size of the transistor, reducing the power consumption and improving the contact performance can be solved.

Disclosed are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises: a second source/drain layer (2), an insulation layer (3) and a first source/drain layer (1), which are sequentially arranged in a stacked manner; and a gate electrode (5) and a channel layer (4) surrounding the gate electrode (5), which are located in the first source/drain layer (1) and the insulation layer (3), wherein the channel layer (4) is in contact with the first source/drain layer (1) and the second source/drain layer (2); the first source/drain layer (1) comprises a first metal layer (11) and a second metal layer (12), the first metal layer (11) is close to the insulation layer (3), and the second metal layer (12) is away from the insulation layer (3); the material of the first metal layer (11) is a metal with a work function lower than that of molybdenum; and the material of the second metal layer (12) is a metal with a conductivity higher than 310.sup.6 S/m and an oxidation resistance not lower than that of molybdenum. By means of the thin-film transistor of a CAA architecture, the size of the transistor can be reduced, the power consumption of the transistor can be reduced, and the contact performance and the conductivity performance of the transistor can be improved.

Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which is located between the first source/drain layer (1) and the second source/drain layer (3); a channel layer (4), which is embedded in the first source/drain layer (1) and the insulating layer (2); and a gate electrode (5), which is embedded in the channel layer (4), wherein an embedded end of the channel layer (4) is in contact with the second source/drain layer (3), and a top end of the channel layer (4) and a top end of the gate electrode (5) are both flush with the first source/drain layer (1). The thin-film transistor provided in the present disclosure is a CAA architecture in which an annular channel is arranged surrounding the gate electrode (5), such that the performance of the transistor can be improved, and the power consumption can be reduced; moreover, there is no gate electrode (5) in the horizontal direction covering the first source/drain layer (1), such that the parasitic capacitance and current leakage of the gate electrode can be reduced.

A transistor having excellent electrical characteristics is provided. The transistor includes an indium oxide film and a metal oxide film over the indium oxide film. A region of the indium oxide film where a channel is formed is a single crystal. The metal oxide film contains indium, gallium, and zinc. The <111> orientation of the single crystal region of the indium oxide film is parallel or substantially parallel to the <001> orientation of a crystal in the metal oxide film. The indium oxide film can be provided over a silicon oxide film or a silicon nitride film. Alternatively, the indium oxide film can be provided over a metal oxide film containing indium, tin, and silicon.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer over the second conductive layer, a semiconductor layer and a third conductive layer over the first insulating layer, a second insulating layer over the semiconductor layer and the third conductive layer, and a fourth conductive layer over the second insulating layer; at least part of the second conductive layer is in contact with a top surface of the first conductive layer; the semiconductor layer is in contact with the top surface of the first conductive layer, a side surface of the second conductive layer, the third conductive layer, and a side surface of the first insulating layer; and the fourth conductive layer overlaps with the semiconductor layer with the second insulating layer therebetween.

A thin film transistor and a preparation method therefor, a memory, and a display. The thin film transistor comprises: a first source/drain layer (1), a first insulating layer (2), a second source/drain layer (3) and a second insulating layer (4) which are sequentially stacked; and a gate (6) and a channel layer (5) surrounding the gate (6), which are located in the second insulating layer (4), the second source/drain layer (3) and the first insulating layer (2). The channel layer (5) is in contact with the first source/drain layer (1), the first insulating layer (2), the second source/drain layer (3) and the second insulating layer (4). The thin film transistor is a CAA architecture of an annular channel surrounding the gate (6). Moreover, the leakage current of the gate (6) and the parasitic capacitance of the thin film transistor can be reduced by adding the second insulating layer (4) above the second source/drain layer (3).

A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, first and second insulating layers, and a wiring. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer includes a first opening reaching the first conductive layer. The semiconductor layer is in contact with the second conductive layer over the first insulating layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The second insulating layer includes a second opening that is in a position overlapping with the first opening and reaches the semiconductor layer. The third insulating layer is in contact with a side surface of the second insulating layer in the second opening and the semiconductor layer in the first opening. The third conductive layer is embedded in the second opening and the first opening. The wiring is positioned over the second insulating layer, is in contact with the third conductive layer, and includes a portion overlapping with the semiconductor layer or the second conductive layer with the second insulating layer therebetween.

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes an oxide semiconductor layer including a plurality of metals, wherein, with respect to the plurality of metals, a content of indium (In) is less than 50 at %, and a content of zinc (Zn) is 0 at %, a gate electrode being apart from the oxide semiconductor layer, a gate insulating layer being between the oxide semiconductor layer and the gate electrode, and a first electrode and a second electrode on the oxide semiconductor layer and being apart from each other with the gate electrode interposed therebetween.

The present disclosure relates to an oxide semiconductor memory device and a manufacturing method thereof, and more particularly, to an oxide semiconductor memory device forming an amorphous indium-gallium-zinc-oxide (hereinafter, referred to as a-IGZO) thin film and a manufacturing method thereof. The present disclosure is to solve a problem of oxide semiconductor forming an a-IGZO thin film having a negative threshold voltage and improve mobility characteristics.