A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.

Provided is a cell layout for a semiconductor device, which includes: a 1.sup.st cell; a 2.sup.nd cell at a side of the 1.sup.st cells in a 1.sup.st direction; and a filler cell between the 1.sup.st cell and the 2.sup.nd cell, wherein each of the 1.sup.st cell, the filler cell, and the 2.sup.nd cell includes a 1.sup.st active pattern and a 2.sup.nd active pattern above the 1.sup.st active pattern in a 3.sup.rd direction, and wherein a width of the 2.sup.nd active pattern and a width of the 1.sup.st active pattern are the same in the filler cell, in a 2.sup.nd direction intersecting the 1.sup.st direction and the 3.sup.rd direction.

Methods for fabricating a semiconductor are disclosed. The methods include creating nanowires of a nanowire type on semiconductor surface, forming grooves in an insulator surface to direct a self-alignment of the nanowires on the insulator surface, converting the insulator surface into the semiconductor of the nanowire type, and isolating the semiconductor by etching the distributed nanowires that are not part of the subset. The converting includes cleaving the nanowires from the semiconductor surface and distributing the nanowires in the grooves, and creating the semiconductor from a subset of the distributed nanowires using a transistor fabrication process.