Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.

A semiconductor device includes a semiconductor body; a gate; a field plate, spaced from the gate, the field plate having a strip-like shape with main extensions along a first direction, the strip-like shape having a first and a second end opposite to one; a first conductive pad in electrical contact with the field plate at the first end through a first connecting region; a second conductive pad in electrical contact with the field plate at the second end through a second connecting region; and a third conductive pad in electrical contact with the field plate at the second end through a third connecting region. The conductive pads allow the use of the field plate as a temperature sensor.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member, a second semiconductor member, a third semiconductor member, and a fourth semiconductor member. The first semiconductor member is of a first conductivity type, and includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The fifth partial region is in Schottky contact with the second electrode. The second semiconductor member is of a second conductivity type, and includes a first portion and a second portion. The third semiconductor member is of the second conductivity type, and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The fourth semiconductor member is of the first conductivity type, and includes a first semiconductor region and a second semiconductor region.

Semiconductor devices and methods, including metal oxide silicon field effect transistor (MOSFET) devices and methods. The semiconductor device, such as a MOSFET, includes two source regions; a drain region; two body regions, and a buffer region. Each of the two body regions contacts a different one of the two source regions. The buffer region is located between the two body regions, and contacts the two body regions. A doping concentration of the buffer region is less than a doping concentration of the two body regions.

A semiconductor device according to some implementations includes a main transistor, a peripheral circuit element connected to one end of the main transistor, and a Zener diode connected between the other end of the main transistor and the peripheral circuit element. The main transistor includes a main channel layer, a barrier layer disposed on the main channel layer, a main gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and a main source electrode and a main drain electrode connected to the main channel layer. The peripheral circuit element includes a sub-channel layer connected to the main drain electrode and including a drift region with a two-dimensional electron gas, and a detection electrode disposed on the sub-channel layer, and the Zener diode is electrically connected between the detection electrode and the main source electrode.

A semiconductor device includes a body, a first electrode, and an insulation layer. The body includes: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed at a position where the second semiconductor region is in contact with the first electrode and the insulation layer; and a third semiconductor region of the first conductive type formed in contact with the second semiconductor region such that the third semiconductor region surrounds the second semiconductor region as viewed in a plan view. In the semiconductor device, assuming a total amount of dopants in the second semiconductor region as S1 and a total amount of dopants in the third semiconductor region as S2, a relationship of S1<S2 is satisfied, and a combination of the second semiconductor region and the third semiconductor region has a function of a Zener diode.

A transistor power device includes: a substrate, having a front surface opposite a rear surface; at least a first trench, which extends within the substrate, a gate region in a surface portion of the first trench; at least a second trench, which extends within the substrate, a first conductive region at a surface portion of the second trench. At least a first surface portion of the first conductive region is doped with a first conductivity type and at least a second surface portion of the first conductive region is doped with a second conductivity type, to respectively define a cathode terminal and an anode terminal of a diode element, integrated in the second trench. A protection element is integrated within the second trench, arranged between the first conductive region and the substrate, forming a shield element for the diode element with respect to the substrate.

The disclosure relates to a semiconductor device (100), comprising: a die layer (110) comprising a top surface and a bottom surface opposing the top surface; wherein the die layer (110) forms a plurality of unit cells (120) arranged side-by-side across the top surface of the die layer (110), wherein each unit cell (120) comprises a sub cell of a first type (120a) and a sub cell of a second type (120b) which are both integrated in the unit cell (120), wherein the sub cell of the first type (120a) comprises a first electrode (121), a second electrode (122) and a third electrode (123) formed at the top surface of the die layer (110), a first one of the three electrodes (121, 122, 123) being arranged to enclose a second one of the three electrodes (121, 122, 123); and the first one and the second one of the three electrodes (121, 122, 123) being arranged to enclose a third one of the three electrodes (121, 122, 123); wherein the sub cells of the first type (120a) form high electron mobility transistor, HEMT, cells; and wherein the sub cells of the second type (120b) form Schottky Barrier Diode, SBD, cells.

A power device includes high electron mobility transistors formed on an active layer, each transistor comprising a source finger, a drain finger and a gate finger, a source contact common to the source fingers, a drain contact common to the drain fingers, and a gate contact common to the gate fingers. At least one gate finger is not connected to the gate contact and forms a Schottky contact with the active layer. This gate finger forms, with the neighbouring drain finger, a Schottky diode configured to measure an operating temperature within the power device.

A super-junction semiconductor device includes a substrate; an active cell disposed on the substrate; an edge termination region configured to surround the active cell; a peripheral region configured to surround the active cell and disposed between the active region and the edge termination region; a first conductivity-type pillar and a second conductivity-type pillar alternately disposed in the active cell, the peripheral region, and the edge termination region; a horizontal-shaped second conductivity-type pillar region disposed on the second conductivity-type pillar in the peripheral region and the edge termination region; and a second conductivity-type charge-sharing region disposed on the horizontal-shaped second conductivity-type pillar region.