The present disclosure relates to a microphone. In some embodiments, the microphone may comprise a substrate, a diaphragm, a backplate, and a sidewall stopper. The substrate has an opening disposed through the substrate. The diaphragm is disposed over the substrate and facing the opening of the substrate. The diaphragm has a venting hole overlying the opening of the substrate. A backplate is disposed over and spaced apart from the diaphragm. A sidewall stopper is disposed along a sidewall of the venting hole of the diaphragm and thus is not limited by a distance between the movable part and the stable part. Also, the sidewall stopper does not alternate the shape of movable part, and thus will less likely introduce crack to the movable part. In some embodiments, the sidewall stopper may be formed like a sidewall stopper by a self-alignment process, such that no extra mask is needed.

A structure forming method according to an aspect is a structure forming method for forming a first hole and a second hole having width smaller than width of the first hole in a substrate with dry etching and forming a structure. The structure forming method includes forming an etching mask on the substrate, etching a portion of the etching mask overlapping a first hole forming region where the first hole is formed, etching a portion of the etching mask overlapping a second hole forming region where the second hole is formed, and performing the dry etching of the substrate using the etching mask as a mask.

A MEMS sensor with improved overload resistance for metrological registering of a measured variable comprises a plurality of layers, especially silicon layers, arranged on one another. The layers include at least one inner layer, which is arranged between a first layer and a second layer, and in the inner layer there is provided extending perpendicularly to the plane of the inner layer through the inner layer at least one cavity, on which borders externally at least sectionally and forming a connecting element, a region of the inner layer, which is connected with the first layer and the second layer. A lateral surface of the connecting element externally at least sectionally bordering the cavity has in an end region facing the first layer a rounding decreasing the cross sectional area of the cavity in the direction of the first layer, and has in an end region facing the second layer a rounding decreasing the cross sectional area of the cavity in the direction of the second layer.

A complementary metal-oxide-semiconductor (CMOS) micro electro-mechanical system (MEMS) microphone and a method for fabricating the same are disclosed. Firstly, a CMOS device including a semiconductor substrate, a first oxide insulation layer, a doped polysilicon layer, a second oxide insulation layer, a patterned polysilicon layer, and a metal wiring layer from bottom to top. The metal wiring layer is formed on the second oxide insulation layer. The patterned polysilicon layer includes undoped polysilicon. Then, a part of the metal wiring layer is removed to form a metal electrode and the semiconductor substrate is penetrated to have a chamber and expose the first oxide insulation layer, thereby forming a MEMS microphone.

Devices, systems and techniques are described for producing and implementing articles and materials having nanoscale and microscale structures that exhibit superhydrophobic, superoleophobic or omniphobic surface properties and other enhanced properties. In one aspect, a surface nanostructure can be formed by adding a silicon-containing buffer layer such as silicon, silicon oxide or silicon nitride layer, followed by metal film deposition and heating to convert the metal film into balled-up, discrete islands to form an etch mask. The buffer layer can be etched using the etch mask to create an array of pillar structures underneath the etch mask, in which the pillar structures have a shape that includes cylinders, negatively tapered rods, or cones and are vertically aligned. In another aspect, a method of fabricating microscale or nanoscale polymer or metal structures on a substrate is made by photolithography and/or nano imprinting lithography.

The present invention relates to a free-standing single crystalline diamond part and a single crystalline diamond part production method. The method includes the steps of: providing a single crystalline diamond substrate or layer; providing a first adhesion layer on the substrate or layer; providing a second adhesion layer on the first adhesion layer: providing a mask layer on the second adhesion layer; forming at least one indentation or a plurality of indentations through the mask layer and the first and second adhesion layers to expose a portion or portions of the single crystalline diamond substrate or layer; and etching the exposed portion or portions of the single crystalline diamond substrate or layer and etching entirely through the single crystalline diamond substrate or layer.

Techniques regarding a vertical nanofluidic channel array are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a semiconductor substrate and a dielectric layer adjacent to the semiconductor substrate. The dielectric layer can comprise a first nanofluidic channel and a second nanofluidic channel. The second nanofluidic channel can be located between the first nanofluidic channel and the semiconductor substrate.

Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

Long term optical memory includes a storage medium composed from an array of silicon nanoridges positioned onto the fused silica glass. The array has first and second polarization contrast corresponding to different phase of silicon. The first polarization contrast results from amorphous phase of silicon and the second polarization contrast results from crystalline phase of silicon. The first and second polarization states are spatially distributed over plurality of localized data areas of the storage medium.

A process for fabricating a symmetrical MEMS accelerometer. A pair of half parts is fabricated by, for each half part: (i) forming a plurality of resilient beams, first connecting parts, second connecting parts, and a plurality of comb structures, by etching a plurality of holes on a bottom surface of a first silicon wafer; (ii) etching a plurality of hollowed parts on a top surface of a second silicon wafer; (iii) forming a silicon dioxide layer on the top and bottom surface of the second silicon wafer; (iv) bonding the bottom surface of the first silicon wafer with the top surface of the second silicon wafer; (v) depositing a layer of silicon nitride on the bottom surface of the second silicon wafer, and removing parts of the silicon nitride layer and silicon dioxide layer on the bottom surface of the second silicon wafer; (vii) deep etching the exposed parts of the bottom surface of the second silicon wafer to the silicon dioxide layer located on the top surface of the second silicon wafer, and reducing the thickness of the first silicon wafer; and (viii) removing the silicon nitride layer, and etching the silicon dioxide to form the mass. The two half parts are then bonded along their bottom surface. The device is deep etched to form a movable accelerometer. A bottom cap is fabricated by hollowing out the corresponding area, and depositing metal as electrodes. The accelerometer is bonded with the bottom cap. Metal is deposited on the first silicon wafer to form electrodes.