A display apparatus includes: a substrate; a pixel electrode above the substrate; a first low reflection layer spaced apart from the pixel electrode at a same layer as the pixel electrode and comprising a lower layer having conductivity and an upper layer above the lower layer; a pixel-defining layer above the first low reflection layer and having an opening exposing at least a part of the pixel electrode; an intermediate layer above the pixel electrode and comprising an organic emission layer; and an opposite electrode above the intermediate layer.

In described examples, a cavity is formed between a substrate and a cap. One or more access holes are formed through the cap for removing portions of a sacrificial layer from within the cavity. A cover is supported by the cap, where the cover is for occulting the one or more access holes along a perspective. An encapsulant seals the cavity, where the encapsulant encapsulates the cover and the one or more access holes.

The present disclosure includes apparatuses and methods related to freezing a sacrificial material in forming a semiconductor. In an example, a method may include solidifying, via freezing, a sacrificial material in an opening of a structure, wherein the sacrificial material has a freezing point below a boiling point of a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to a particular temperature range.

Methods for depositing a measured amount of a species in a sealed cavity. In one example, a method for depositing molecules in a sealed cavity includes depositing a selected number of microcapsules in a cavity. Each of the microcapsules contains a predetermined amount of a first fluid. The cavity is sealed after the microcapsules are deposited. After the cavity is sealed the microcapsules are ruptured to release molecules of the first fluid into the cavity.

A method for producing a particle protection element. The method include: providing a substrate; applying a first silicon dioxide layer to a surface of the substrate and structuring the first SiO2 layer, a height of a later plurality of media passage structures of the particle protection element, which form a filter function with respect to penetrating particles, can be set based on a thickness of the first SiO2 layer; depositing a first polysilicon layer onto a surface of the first silicon dioxide layer and/or of the substrate, and structuring the first poly-Si layer for forming a later at least one first channel structure; and forming a later at least one second channel structure on the rear side of the substrate, wherein the later first channel structure and/or the later media passage structures and/or the later second channel structure are connectable with regard to a media flow.

The method according to the invention is used for producing optical components, in particular covers for encapsulating micro-systems, wherein at least one reinforcing element, which is produced before being arranged, is arranged on a first substrate, as a result of which a stack is produced. This stack is heated after being connected to a second substrate, as a result of which the first substrate is deformed such that at least one region, covered by the reinforcing element, of the first substrate is moved and/or is inclined or the first substrate is brought into contact with the reinforcing element. In an alternative method according to the invention, the reinforcing element is arranged on the second substrate, wherein this stack is then connected to the first substrate. The first substrate is subsequently heated and deformed such that a region of the first substrate is brought into contact with the reinforcing element.

A method of preventing corrosion associated with an electrically-conductive through-glass via (TGV) may comprise forming a TGV in a glass substrate for use in a microelectromechanical system (MEMS) device. The TGV has a first end and a second end, and at least partially comprises copper. The method may further comprise applying a conductive barrier layer on the first end of the TGV and/or the second end of the TGV, and applying a metal layer over the conductive barrier layer. The method may further comprise extending the conductive barrier layer over the first end of the TGV, and over at least a portion of the glass substrate encompassing the end of the TGV, such that the conductive barrier layer overlaps a boundary between the TGV and the glass substrate.

An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.

A method for forming a micro-electro mechanical system (MEMS) device is provided. The method includes forming a first dielectric layer over a semiconductor layer and forming a blocking layer over the first dielectric layer. The method also includes bonding a CMOS substrate with the blocking layer, and the CMOS substrate includes a second dielectric layer, and the blocking layer is configured to block gas coming from the second dielectric layer. The method further includes partially removing the first dielectric layer to form a cavity between the semiconductor layer and the blocking layer. A portion of the semiconductor layer above the cavity becomes a movable element. In addition, the method includes sealing the cavity such that a closed chamber is formed to surround the movable element.

A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer.