A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.

Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

Various embodiments of the present disclosure are directed towards an integrated chip including a capping structure over a device substrate. The device substrate includes a first microelectromechanical systems (MEMS) device and a second MEMS device laterally offset from the first MEMS device. The capping structure includes a first cavity overlying the first MEMS device and a second cavity overlying the second MEMS device. The first cavity has a first gas pressure and the second cavity has a second gas pressure different from the first cavity. An outgas layer abutting the first cavity. The outgas layer includes an outgas material having an outgas species. The outgas material is amorphous.

A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device monolithically after CMOS processing. For example, the MEMS sensors are formed over a BEOL dielectric of a CMOS device. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region.

The invention relates to antenna apparatus comprising: an antenna, a signal conductor and one or more RF MEMS switches, the antenna being conductively connected to the signal conductor, the MEMS switches and at least a portion of the signal conductor being supported by a crystalline MEMS substrate; and a capping substrate comprising a capping portion, wherein an enclosed volume is formed around the said MEMS switches between the capping portion and at least a portion of the crystalline MEMS substrate, and wherein the capping substrate comprises the said antenna.

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

A complementary metal oxide semiconductor (CMOS) device integrated with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device heterogeneously. For example, a CMOS wafer with CMOS devices and interconnections as well as partially processed MEMS modules is bonded with a MEMS wafer with MEMS structures, post CMOS compatibility issues are alleviated. Post integration process to complete the devices includes forming contacts for interconnecting the sensors to the CMOS components as well as encapsulating the devices with a cap wafer using wafer-level vacuum packaging.

An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.

According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein.