Ultrasonic sensing approaches are described with integrated MEMS-CMOS implementations. Embodiments include ultrasonic sensor arrays for which PMUT structures of individual detector elements are at least partially integrated into the CMOS ASIC wafer. MEMS heating elements are integrated with the PMUT structures by integrating under the PMUT structures in the CMOS wafer and/or over the PMUT structures (e.g., in the protective layer). For example, embodiments can avoid wafer bonding and can reduce other post processing involved with conventional manufacturing of PMUT ultrasonic sensors, while also improving thermal response.

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

In a microelectromechanical component according to the invention, at least one microelectromechanical element (5), electrical contacting elements (3) and an insulation layer (2.2) and thereon a sacrificial layer (2.1) formed with silicon dioxide are formed on a surface of a CMOS circuit substrate (1) and the microelectromechanical element (5) is arranged freely movably in at least a degree of freedom. At the outer edge of the microelectromechanical component, extending radially around all the elements of the CMOS circuit, a gas- and/or fluid-tight closed layer (4) which is resistant to hydrofluoric acid and is formed with silicon, germanium or aluminum oxide is formed on the surface of the CMOS circuit substrate (1).

Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.

A method includes obtaining an active device layer. The active device layer has a first surface with one or more active feature areas. First portions of the active feature areas are exposed, and second portions of the active feature areas are covered by an insulating layer. A conformal overcoat layer is formed on the first surface. A base of a microelectromechanical systems (MEMS) device layer is formed on the conformal overcoat layer. The MEMS device layer is spatially segregated from the active feature areas by removing portions of the base of the MEMS device layer in one or more antiparasitic regions (APRs) that correspond to the active feature areas. Metal MEMS features are formed on the base of the MEMS device layer. Selected portions of the active feature areas are exposed removing portions of the conformal overcoat layer that overlay the active feature areas.

A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.

An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

An integrated semiconductor device includes: a MEMS structure; an ASIC electronic circuit; and conductive interconnection structures electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

An optical electronics device includes first, second and third wafers. The first wafer has a semiconductor substrate with a dielectric layer on a side of the semiconductor substrate. The second wafer has a transparent substrate with an anti-reflective coating on a side of the transparent substrate. The first wafer is bonded to the second wafer at a silicon dioxide layer between the semiconductor substrate and the anti-reflective coating. The first and second wafers include a cavity extending from the dielectric layer through the semiconductor substrate and through the silicon dioxide layer to the anti-reflective coating. The third wafer includes micromechanical elements. The third wafer is bonded to the dielectric layer, and the micromechanical elements are contained within the cavity.