A thin film deposition system deposits a thin film on a substrate in a thin film deposition chamber. The thin film deposition system deposits the thin film by flowing a fluid into the thin film deposition chamber. The thin film deposition system includes a byproducts sensor that senses byproducts of the fluid in an exhaust fluid. The thin film deposition system adjusts the flow rate of the fluid based on the byproducts.

A semimetal liner and a metal-insulator-metal (MIM) capacitor (MIMCAP) are described along with the methods of manufacture or fabrication. The MIM capacitor structure includes a liner formed of a thin layer or film of a semimetal, which is a few nanometers thick, e.g., a thickness in the range of about 0.5 nm to about 5 nm or more. The semimetal liner is sandwiched between an electrode layer and a dielectric layer, e.g., a layer of high or ultra-high-k material, thereby providing a cap for the electrode to limit leakage currents in the structure.

Disclosed is a method for manufacturing an aluminum precursor formed by mixing 1 to 3 moles of a compound represented by the following Chemical Formula 1 or following Chemical Formula 2 and 1 to 3 moles of a compound represented by the following Chemical Formula 3,

##STR00001## wherein X is O or S, and R1 or R2 is each independently selected from an alkyl group having 1 to 8 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, and an aryl group having 6 to 12 carbon atoms,

##STR00002## wherein X is O or S, n is 1 to 5, and R1 to R4 are each independently selected from a hydrogen atom, an alkyl group having 1 to 5 carbon atoms, a cycloalkyl group having 3 to 6 carbon atoms, and an aryl group having 6 to 12 carbon atoms,

##STR00003## wherein R1, R2 and R3 are different from each other, and each independently selected from a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, a dialkylamine having 1 to 6 carbon atoms, a cycloamine group having 1 to 6 carbon atoms, or a halogen atom.

An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Vapor deposition methods and related systems are provided for depositing layers comprising vanadium and oxygen. In some embodiments, the methods comprise contacting a substrate in a reaction space with alternating pulses of a vapor-phase vanadium precursor and a vapor-phase oxygen reactant. The reaction space may be purged, for example, with an inert gas, between reactant pulses. The methods may be used to fill a gap on a substrate surface. Reaction conditions, including deposition temperature and reactant pulse and purge times may be selected to achieve advantageous gap fill properties. In some embodiments, the substrate on which deposition takes place is maintained at a relatively low temperature, for example between about 50 C. and about 185 C.

A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

A semiconductor device in which variation in electrical characteristics is small is provided. A first insulator is deposited, a metal oxide is device over the first insulator, a second insulator is device over the metal oxide, an oxide film is device over the second insulator, and heat treatment is performed, whereby hydrogen in the first insulator, the second insulator, and the oxide is transferred and absorbed into the metal oxide. The metal oxide is formed by an ALD method.

A method for treating surface of substrate, the method including forming a film including a high molecular weight condensate of a silylation agent on the surface thereof to allow a substrate having a plurality of regions to be modified at modification degrees that are different depending on materials of the regions on a surface of the substrate. The method includes preparing a substrate having a surface including two or more regions having different materials; exposing the surface to a surface treatment agent; and baking the substrate, the method not including rinsing the surface with a liquid between the exposing and the baking, the surface treatment agent including a silylation agent and not a nitrogen-containing heterocyclic compound, the silylation agent including organomonosilane that has 2 to 4 nitrogen atoms bonded to a silicon atom.

Methods for selective deposition of silicon oxide films on metal or metallic surfaces relative to dielectric surfaces are provided. A dielectric surface of a substrate may be selectively passivated relative to a metal or metallic surface, such as by exposing the substrate to a silylating agent. Silicon oxide is then selectively deposited on the metal or metallic surface relative to the passivated oxide surface by contacting the metal surface with a metal catalyst and a silicon precursor comprising a silanol.

A manufacturing method of a semiconductor device includes depositing, using a first atomic layer deposition, a first thin poly silicon layer on an active area, in which the active area includes a trench; depositing, using a second atomic layer deposition, a second thin poly silicon layer on the active area; and depositing, using a chemical vapor deposition, a poly silicon layer on the active area to form a poly silicon structure, in which a gas for the chemical vapor deposition includes disilane, a thickness of the poly silicon layer in a bottom of the trenches is substantially zero.