SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD BASED ON SEEDLESS SILICON SOURCE/DRAIN CONTACT RESISTANCE REDUCTION AND LASER PROCESS TECHNOLOGY

Abstract

Disclosed are a semiconductor device based on seedless silicon (Si) source/drain contact resistance reduction and laser process technology and a method of fabricating the same. The semiconductor device includes an activated seedless Si layer formed on a substrate and at least one electrode formed on the seedless Si layer, and the seedless Si layer is crystalized through a first laser process and then activated through a second laser process.

Claims

1. A semiconductor device comprising: an activated seedless silicon (Si) layer formed on a substrate; and at least one electrode formed on the seedless Si layer, wherein the seedless Si layer is crystalized through a first laser process and is activated through a second laser process.

2. The semiconductor device of claim 1, wherein the substrate is an interlayer dielectric (ILD) deposited on a bottom device layer in a monolithic three-dimensional (3D) (M3D) integration structure.

3. The semiconductor device of claim 2, wherein the first laser process uses a continuous wavelength (CW) laser with the wavelength of about 532 nm, and the second laser process uses a pulsed laser with the wavelength of about 355 nm.

4. The semiconductor device of claim 3, wherein the semiconductor device is a transistor or a metal-oxide-semiconductor field effect transistor (MOSFET).

5. A method of fabricating a semiconductor device, the method comprising: forming a seedless silicon (Si) layer on a substrate; crystalizing the seedless Si layer through a first laser process; forming a buffer layer on the seedless Si layer; implanting dopant into the seedless Si layer; activating the dopant through a second laser process; removing the buffer layer; and forming an electrode on the seedless Si layer.

6. The method of claim 5, wherein the substrate is an interlayer dielectric (ILD) deposited on a bottom device layer in a monolithic three-dimensional (3D) (M3D) integration structure.

7. The method of claim 6, wherein the first laser process uses a continuous wavelength (CW) laser with the wavelength of about 532 nm, the second laser process uses a pulsed laser with the wavelength of about 355 nm, and the buffer layer includes tetraethyl orthosilicate (TEOS).

8. The method of claim 7, wherein the dopant is boron (B) or phosphorus (P).

9. The method of claim 8, wherein the electrode includes NiSi, Ti, and Au or Ti and Au that are sequentially stacked.

10. The method of claim 9, wherein the electrode includes a source electrode, a drain electrode, and a gate electrode, the source electrode and the drain electrode include NiSi, Ti, and Au that are sequentially stacked, and the gate electrode includes Ti and Au that are sequentially stacked.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] These and/or other aspects, features, and advantages of the invention will become apparent and more readily appreciated from the following description of example embodiments, taken in conjunction with the accompanying drawings of which:

[0017] FIG. 1 illustrates a semiconductor device according to an example embodiment;

[0018] FIG. 2 is a schematic process diagram of the semiconductor device illustrated in FIG. 1;

[0019] FIG. 3 is a flowchart illustrating a method of fabricating the semiconductor device illustrated in FIG. 1;

[0020] FIG. 4 illustrates the results of performing secondary ion mass spectrometry (SIMS) analysis after performing an ion implantation process;

[0021] FIG. 5 illustrates an image of patterned seedless silicon (Si) for results of a surface ablation test according to the laser power for dopant activation;

[0022] FIG. 6 illustrates the results of surface resistance and SIMS analysis using a 4-point-probe (4pp) method after laser activation;

[0023] FIG. 7 illustrates I/V characteristics in a metal-semiconductor (MS) contact structure after a laser activation process; and

[0024] FIG. 8 illustrates I/V characteristics of MS structure seedless Si to which an optimized laser activation process condition is applied.

DETAILED DESCRIPTION

[0025] The aforementioned features and effects of the disclosure will be apparent from the following detailed description related to the accompanying drawings and accordingly those skilled in the art to which the disclosure pertains may easily implement the technical spirit of the disclosure.

[0026] Various modifications and/or alterations may be made to the disclosure and the disclosure may include various example embodiments. Therefore, some example embodiments are illustrated as examples in the drawings and described in detailed description. However, they are merely intended for the purpose of describing the example embodiments described herein and may be implemented in various forms. Therefore, the example embodiments are not construed as limited to the disclosure and should be understood to include all changes, equivalents, and replacements within the idea and the technical scope of the disclosure.

[0027] Although terms of first, second, and the like are used to explain various components, the components are not limited to such terms. These terms are used only to distinguish one component from another component.

[0028] For example, a first component may be referred to as a second component, or similarly, the second component may be referred to as the first component within the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0029] As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components or a combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0030] Hereinafter, example embodiments will be described with reference to the accompanying drawings. However, the scope of the patent application is not limited to or restricted by such example embodiments. Like reference numerals used herein refer to like elements throughout.

[0031] FIG. 1 illustrates a semiconductor device according to an example embodiment.

[0032] Referring to FIG. 1, the semiconductor device includes a transistor, a field effect transistor (FET), a metal-oxide-semiconductor FET (MOSFET), an inverter, a memory device, and a complementary metal-oxide-semiconductor (CMOS) device. The semiconductor device includes a substrate, an active layer, and at least one top electrode.

[0033] The substrate refers to a silicon (Si) substrate and may be implemented with SiO.sub.2. Also, the substrate may function as an interlayer dielectric (ILD). In this case, an ILD layer is provided on a bottom device layer in a monolithic 3D (M3D) integration structure, and the bottom device layer and a top device layer are separated based on the ILD layer. According to an example embodiment, the ILD layer may have a thickness of about 200 nm.

[0034] The active layer formed on the substrate refers to an activated seedless Si layer, and may have a thickness of about 110 nm according to an example embodiment.

[0035] At least one top electrode formed on the active layer includes at least one of a source electrode, a drain electrode, and a gate electrode. According to an example embodiment, the source electrode and the drain electrode may be formed to be spaced apart from the gate electrode by providing the gate electrode therebetween. The at least one electrode may be implemented as a single layer, or may have a hierarchical structure that includes a plurality of layers. In the case of the hierarchical structure, a structure in which NiSi, Ti (or Mo), and Au are stacked or a structure in which Ti (or Mo) and Au are stacked from the active layer may be utilized. Also, depending on example embodiments, at least some of the plurality of layers may be omitted and/or the order between the layers may be changed.

[0036] FIG. 2 is a schematic process diagram of the semiconductor device illustrated in FIG. 1, and FIG. 3 is a flowchart illustrating a method of fabricating the semiconductor device illustrated in FIG. 1.

[0037] Referring to FIGS. 1 to 3, an additional operation or process may be applied between operations specified in a process of fabricating the semiconductor device and the present invention does not exclude application of this additional operation or process. Also, the present invention may refer to an M3D top device or a top CMOS device and a method of fabricating the same.

[0038] In operation S110, a substrate is prepared. The substrate may be formed by depositing a Si substrate on a bottom device layer (e.g., bottom MOSFET layer) as an ILD layer. The ILD layer may electrically isolate the top device layer and/or the bottom device layer by electrically separating the bottom device layer and the top device layer.

[0039] In operation S120, a seedless Si layer is formed on the substrate. The seedless Si layer may be formed by depositing seedless Si on the substrate.

[0040] In operation S130, a crystallization is performed on the seedless Si layer. When crystallizing amorphous silicon using a laser, seedless Si may be crystallized using a continuous wavelength (CW) laser with the wavelength of about 532 nm according to an example embodiment.

[0041] In operation S140, a buffer layer, also called a screen layer, is formed. According to an example embodiment, the buffer layer may be formed by depositing tetraethyl orthosilicate (TEOS) with the thickness of about 10 nm on the seedless Si layer.

[0042] In operation S150, an ion implantation (or ion injection) process is performed. Exemplary conditions of the ion implantation process for implanting dopant are presented in Table 1 below.

TABLE-US-00001 TABLE 1 Dose Power Substrate ILD Dopant (cm.sup.2) (keV) Si PECVD SiO.sub.2 Boron 5.0 10.sup.15 10 (200 nm) Phosphorous 15

[0043] The results of performing secondary ion mass spectrometry (SIMS) analysis after performing the ion implantation process using the conditions of Table 1 are shown in FIG. 4. Referring to FIG. 4, it can be seen that doping concentration peak appears within the depth of about 110 nm or less, the thickness of the top device (, which may indicate seedless Si layer).

[0044] In operation S160, an activation for the seedless Si layer is performed. According to an example embodiment, a pulsed laser with the wavelength of about 355 nm (more specifically, Nd:YAG 355-nm pulsed layer) may be used to electrically activate the dopant implanted into the seedless Si layer. By optimizing process conditions of the pulsed laser, the surface of seedless Si damaged by kinetic energy in the ion implantation process may be recrystallized.

[0045] This laser activation process may activate more dopant since the more heat is generated as the laser power increases. However, if the generated heat is excessive, a surface ablation phenomenon that the surface burns may occur, which may deteriorate the electrical property. Therefore, to search for the optimal laser activation power conditions for S/D dopant activation, a surface ablation test was performed by splitting the laser power as shown in Table 2.

TABLE-US-00002 TABLE 2 Laser Beam scan Beam Laser power speed size Substrate ILD Dopant type (mJ/cm.sup.2) (mm/s) (um) Si PECVD Boron Nd: YAG 80 0.3 150 10 SiO.sub.2 355 nm 100 (50 nm) Phosphorus 30 ns 120 70 kHz 140 Top-Hat 160 beam

[0046] In this regard, FIG. 5 illustrates an image of patterned seedless Si for results of the surface ablation test according to the laser power. Referring to FIG. 5, for the laser power of 80 mJ/cm.sup.2, the dopant activation effect is expected to be insignificant since no significant color change is observed compared to non-laser-activated Si. For the laser power of 160 mJ/cm.sup.2, a relatively distinct color change is observed compared to non-laser-activated Si, but thermal damage is identified with the naked eye at the Si edge, which may deteriorate the electrical property.

[0047] Therefore, conditions of 100, 120, and 140 mJ/cm.sup.2 are adopted to search for the optimal laser power. After laser activation is performed using the adopted conditions, surface resistance is extracted using a 4-point-probe (4pp) method to search for the optimal conditions.

[0048] Using the sheet resistance measurement results, the dopant concentration was calculated for each laser power condition, and as shown in FIG. 6, it was about 10.sup.20 cm.sup.3 under all conditions, which satisfies a desired reference value (N>10.sup.18 cm.sup.3). Also, as shown in FIG. 6, the lowest sheet resistance and the highest sheet resistance were measured at the laser power of 140 mJ/cm.sup.2 and at the laser power of 100 mJ/cm.sup.2, respectively.

[0049] To analyze a dopant profile after laser activation, SIMS analysis was performed at the maximum laser power (140 mJ/cm.sup.2) among the conditions adopted as shown in FIG. 6, which was verified to be consistent with the doping concentration calculation results through 4pp measurement. It was verified that neither top P-type Si nor N-type type Si exhibited excessive diffusion at the given laser power, and that the doping concentration peak appears within the depth of about 100 nm or less.

[0050] Electrical characteristic evaluation was performed to verify the optimal laser power conditions based on analysis data. As shown in FIG. 7, both P-type and N-type exhibited the highest conductivity at the maximum laser power (140 mJ/cm.sup.2), which is consistent with the trend of sheet resistance values measured at different laser power using the 4pp method. Therefore, it may be determined that the S/D area contact resistance of seedless Si will be lowest at the laser power of 140 mJ/cm.sup.2.

[0051] As shown in FIG. 8, the contact resistance in the MS structure to which an e-beam evaporated Ti metal was applied was extracted using a transmission line metal (TLM) pattern under the corresponding laser power conditions. Table 3 below presents the contact resistance analysis results of the MS-structured seedless Si using the optimized laser activation process conditions. As shown in Table 3, the contact resistance of top Si was extracted as 2.6310.sup.6 for P-type and was extracted as 1.4010.sup.6 .Math.cm.sup.2 for N-type.

TABLE-US-00003 TABLE 3 Laser power Scan speed Contact resistance Dopant type (mj/cm.sup.2) (mm/s) ( .Math. cm.sup.2) P-type 140 0.3 2.63 10.sup.6 N-type 1.40 10.sup.6

[0052] Referring again to FIGS. 1 to 3, in operation S170, the buffer layer is removed. The buffer layer may be removed through a physical and/or chemical method. For example, by immersing a semiconductor device being fabricated in buffered oxide etchant (BOE) for a predetermined period of time (e.g., 10 seconds), only the buffer layer may be selectively removed.

[0053] In operation S180, at least one electrode is formed. The at least one electrode includes at least one of a source electrode, a drain electrode, and a gate electrode. The at least one electrode may be formed by depositing predetermined at least one metal on the seedless Si layer.

[0054] Here, to acquire lower contact resistance, NiSi may be applied to an S/D contact. When forming NiSi, 450 C., 30 sec conditions may be applied to evaporated Ni 15 nm using RTA.

[0055] As described above, according to example embodiments, it is possible to fabricate a semiconductor device through two laser processes without high-temperature processing.

[0056] While this disclosure includes specific example embodiments, it will be apparent to one of ordinary skill in the art that various alterations and modifications in form and details may be made in these example embodiments without departing from the spirit and scope of the claims and their equivalents. For example, suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents.

[0057] Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.