A semiconductor arrangement includes first and second controllable semiconductor devices forming a half-bridge arrangement, each controllable semiconductor device including a control electrode and a controllable load path between a first load electrode and a second load electrode. At least one gate driver is configured to generate one or more control signals for one or more of the controllable semiconductor devices. The first controllable semiconductor device is arranged on and electrically coupled to a first lead frame of a plurality of lead frames. The second controllable semiconductor device is arranged on and electrically coupled to a second lead frame of the plurality of lead frames. The controllable semiconductor devices and the at least one gate driver are arranged in a molded package. Each lead frames is partly covered by the molded package and has at least one surface or section that is not covered by the molded package.

Even if there is a change in the shape of a transfer mold power module is required, a change in a position of the electrode of the module is facilitated by separating electrode terminals of a power module from the electrodes and retrofitting the separated electrode terminals to the electrodes with high precision. A semiconductor device includes a mold resin enclosing a semiconductor chip, an electrode electrically connected to the semiconductor chip and exposed in an opening provided in the mold resin, and an electrode terminal having a contact portion that covers the electrode and is in electrical contact with the electrode, a plurality of projections formed to surround the contact portion and provided between a side surface of the opening and the contact portion, a contact end portion having the contact portion and an open end portion which is a different end portion from the contact end portion.

A package and method is disclosed. In one example, the package comprises a carrier comprising a component mounting area from which a tie bar extends, the tie bar being configured for being clamped by an encapsulation tool pin during encapsulation, an electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier, wherein a sidewall of the package has a step between a first vertical sidewall section and a second vertical sidewall section; wherein the first vertical sidewall section has a notch in the encapsulant and a part of the second vertical sidewall section exposes the tie bar.

A semiconductor arrangement includes first and second semiconductor packages separate from one another. Each semiconductor package includes a die carrier having opposite first and second main faces, a transistor die disposed on the first main face, a first lead connected to a first load electrode of the transistor die, a second lead connected to a gate electrode of the transistor die, and an encapsulant embedding at least part of the first main face of the die carrier, inner portions of the leads and the transistor die. The first lead of the first semiconductor package is electrically connected to the first lead of the second semiconductor package, forming a source-source connection. The second lead of the first semiconductor package and the second lead of the second semiconductor package are arranged between the first semiconductor package and the second semiconductor package.

A transistor package includes a semiconductor transistor chip having opposite first and second surfaces, one or a plurality of first load electrodes, one or a plurality of second load electrodes, and a control electrode on the first surface. A leadframe faces the first surface of the semiconductor transistor chip and includes a first terminal, a second terminal, and a control terminal of the package which are exposed at a bottom of the package. The first terminal is electrically coupled to the first load electrode(s). The second terminal is electrically coupled to the second load electrode(s). The control terminal is electrically coupled to the control electrode. The first terminal is aligned with a first side of the package. The second terminal is aligned with a second side opposite the first side. The control terminal is aligned with a third side of the package which connects between the first and second sides.

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

A semiconductor device includes: a first lead including a base portion; a semiconductor element mounted on a first side of the base portion in the thickness direction and including a first electrode; a second lead spaced apart from the base portion in a first direction perpendicular to the thickness direction; a first conductive member electrically bonded to the first electrode and the second lead; and a sealing resin. The first conductive member includes a first portion bonded to the first electrode via a conductive first bonding layer. The first portion includes a first surface and a second surface respectively facing the first side and a second side in the thickness direction. The first portion includes a plurality of first recesses that are recessed from the first surface and a plurality of second recesses that are recessed from the second surface.

A semiconductor device includes an active layer having an active region, a source electrode and a drain electrode disposed on the active region of the active layer and extending along a first direction, a source metal layer disposed on the active region and electrically connected to the source electrode, a drain metal layer disposed on the active region and electrically connected to the drain electrode, and a source pad disposed on the active region. The source metal layer extends along a first direction and has a trapezoid shape in a plan view. The drain metal layer extends along the first direction and has a trapezoid shape in the plan view. The source pad is electrically connected to the source metal layer, and the source pad includes a body portion extending along a second direction and a branch portion extending along the first direction.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.