A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.

A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and on the bottom portion; an isolation layer positioned in the substrate; an air gap structure positioned in the isolation layer; and an in-recess spacer positioned in the substrate, surrounding the bottom portion and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the sealed cavities.

Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes receiving a fin-shaped structure comprising a first channel region and a second channel region, a first and a second dummy gate structures disposed over the first and the second channel regions, respectively. The method also includes removing a portion of the first dummy gate structure, a portion of the first channel region and a portion of the substrate under the first dummy gate structure to form a trench, forming a hybrid dielectric feature in the trench, removing a portion of the hybrid dielectric feature to form an air gap, sealing the air gap, and replacing the second dummy gate structure with a gate stack after sealing the air gap.

A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

A semiconductor device includes a fin on a substrate extending along a fin direction, a first and a second source/drain features on the fin. The semiconductor device also includes a stack of semiconductor layers over a first portion of the fin and between the first source/drain feature and the second source/drain feature. The semiconductor device further includes a gate structure over the stack of semiconductor layers. The gate structure extends along a gate direction perpendicular to the fin direction. Moreover, the gate structure engages with the stack of semiconductor layers. The semiconductor device includes a dielectric layer interposing between the first source/drain feature and the fin along a vertical direction, where the vertical direction is perpendicular to the fin direction and to the gate direction. The dielectric layer interfaces with the first portion of the fin and isolates the first source/drain feature from the first portion of the fin.

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a first and a second raw stack of nanosheets on a substrate; forming a sacrificial gate surrounding the first and second raw stacks of nanosheets; forming a sidewall spacer at a sidewall of the sacrificial gate; forming a buffer layer at sidewalls of the first and second raw stacks of nanosheets; forming an isolation layer between the buffer layers at the sidewalls of the first and second raw stacks of nanosheets; removing the buffer layer and the first and second raw stacks of nanosheets to create a first and a second opening; and forming a first and a second source/drain region in the first and second openings. A structure formed thereby is also provided.