A method includes forming a semiconductor layer on a donor substrate, the semiconductor layer comprising a semiconductor material, forming an array of cavities in the semiconductor layer, bonding a transistor substrate to the semiconductor layer, wherein the transistor substrate encloses the array of cavities to form an array of enclosed voids, performing a separation process to separate (a) the transistor substrate and a first portion of the semiconductor layer including the array of enclosed voids from (b) the donor substrate and a second portion of the semiconductor layer, and using the transistor substrate and the first portion of the semiconductor layer to form a high-electron-mobility transistor (HEMT) device with a two-dimensional electron gas (2DEG) channel region over the array of enclosed voids.

A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.

A method for forming an SOI substrate includes following operations. A first semiconductor layer, a second semiconductor layer and a third semiconductor layer are formed over a first substrate. A plurality of trenches and a plurality of recesses are formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer. The plurality of trenches extend along a first direction, and the plurality of recesses extend along a second direction different from the first direction. The plurality of trenches and the plurality of recesses are sealed to form a plurality of voids. A device layer is formed over the first substrate. The devices layer is bonded to an insulator layer over a second substrate. The third semiconductor layer, the device layer the insulator layer and the second substrate are separated from the first semiconductor layer and the first substrate. The device layer is exposed.

A semiconductor device includes active patterns that include a first-first active pattern, a second-first active pattern, and a third-first active pattern, a back gate electrode extending between the first-first active pattern and the second-first active pattern and extending in the first direction, a first word line and a second word line extending between the second-first active pattern and the third-first active pattern and spaced apart from each other in the second direction, an insulating pattern between the first word line and the second word line, a first air gap between the first-first active pattern and the second-first active pattern, where the back gate electrode is on the first air gap, and a second air gap between the second-first active pattern and the third-first active pattern, where the first word line, the second word line, and the insulating pattern are on the second air gap.

A method of processing a substrate having a gap includes loading the substrate onto a substrate support unit, supplying an oligomeric silicon precursor and a nitrogen-containing gas to the substrate through a gas supply unit on the substrate support unit, and generating a direct plasma in a reaction space by applying a voltage to at least one of the substrate support unit and the gas supply unit, wherein a plurality of sub-steps are performed during the supplying of the oligomeric silicon precursor and the nitrogen-containing gas and the generating a direct plasma, and different plasma duty ratios are applied during the plurality of sub-steps.

Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature.

A circuit structure and a method of manufacturing a circuit structure are provided. The circuit structure includes a first metal line and a second metal line. The second metal line is disposed over the first metal line. At least one air gap is disposed between the first metal line and the second metal line.

A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, arranged from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

A semiconductor structure includes a source/drain feature, a gate structure disposed adjacent to the source/drain feature, a source/drain contact disposed over and electrically connected to the source/drain feature, an interlayer dielectric (ILD) layer over the source/drain feature and adjacent to the source/drain contact and the gate structure, and an air gap surrounding the source/drain contact and separating the source/drain contact from the ILD layer and the gate structure in a top view.