A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

A capacitive isolator is developed. Embodiments of the capacitive isolator include a substrate; a shallow trench isolation region coupled to the substrate; a polysilicon layer disposed above the shallow trench isolation region; a bottom metal plate disposed above the polysilicon layer; one or more lower dielectric layers above the bottom metal plate; an intermediate metal plate disposed above the one or more lower dielectric layers; and a top metal plate disposed above the intermediate metal plate. A semiconductor device including two capacitive isolators and an isolation structure disposed between the two capacitive isolators is also developed.

A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.

A transistor structure and a manufacturing method thereof are provided. The transistor structure includes a gate, doped regions and a gate dielectric structure. The gate is disposed on a substrate and includes a first portion and a second portion, wherein the second portion surrounds the first portion, and a material of the first portion is different from a material of the second portion. The doped regions are disposed in the substrate on both sides of the gate. The gate dielectric structure is disposed between the gate and the substrate.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

A semiconductor device includes a plurality of first resistor elements, an insulating layer and a plurality of second resistor elements. The plurality of first resistor elements are disposed at a side of a main surface of a semiconductor substrate, extending in a first direction parallel to the main surface of the semiconductor substrate, arranged in a second direction parallel to the main surface of the semiconductor substrate and intersecting with the first direction. The insulating layer is disposed at the side of the main surface of the semiconductor substrate between the respective plurality of first resistor elements and having an electrode installation surface in contact with the electrode layer. The plurality of second resistor elements are disposed on the electrode installation surface of the insulating layer between the plurality of first resistor elements, extending in the first direction, arranged in the second direction.

A method of manufacturing a semiconductor structure is disclosed. The semiconductor structure includes a transistor area, which includes a first source-drain area and a word line region. The method includes forming an active layer on a substrate, and the active layer of the transistor region includes a plurality of active structures. A dummy word line structure covering the active structure of the same layer is formed in the first source drain region and the word line region. The first isolation layers arranged alternately with the dummy word line structures in the third direction are formed. Then the dummy word line structure is removed. An initial dielectric layer is formed on the surface of the active structure of the first source-drain region and the word line region. An initial word line is formed on the surface of the initial dielectric layer. The initial word line and the initial dielectric layer located in the first source and drain region are removed.

A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

A method includes depositing a silicon layer over a semiconductor region, forming dielectric isolation regions extending into the silicon layer and the semiconductor region, and recessing the dielectric isolation regions. A first portion of the silicon layer and a second portion of the semiconductor region are between the dielectric isolation regions, and protrude higher than top surfaces of the dielectric isolation regions to form a semiconductor fin. The semiconductor fin is thinned, and after the first semiconductor fin is thinned, the first portion of the silicon layer remains. A gate stack is formed on the semiconductor fin.

A semiconductor device includes a substrate having a first conductivity type and an epitaxial layer disposed on the substrate. A first trench and a second trench are disposed in the epitaxial layer. A first body region and a second body region both having a second conductivity type are disposed in the epitaxial layer, and located on two sides of the first trench, respectively. A first source region and a second source region both having the first conductivity type are disposed on the first body region and the second body region, respectively. A first electrode is disposed in the first trench. A source contact structure includes a first portion disposed in the first trench and is electrically connected to the first source region and the second source region. A first gate is disposed in the second trench.