A method of manufacturing a semiconductor device having a combination structure of a horizontal oxide layer structure and a vertical oxide layer structure, can include: etching from an upper surface of the semiconductor substrate to inside of the semiconductor substrate to form a trench; depositing oxides in the trench to form the vertical oxide layer structure; etching the vertical oxide layer structure from an upper surface thereof to decrease height of the vertical oxide layer structure, and to make a top surface of the vertical oxide layer structure be below the upper surface of the semiconductor substrate, in order to expose side surfaces of the trench; and forming, by an oxidation process, the horizontal oxide layer structure to cover part of the upper surface of the semiconductor substrate and the upper surface of the vertical oxide layer structure.

A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

A semiconductor device manufacturing method includes: forming an organic film composed of a polymer having a urea bond in a recess by supplying amine and isocyanate to a surface of a substrate having the recess; performing a predetermined process on the substrate on which the organic film is formed in the recess; and removing the organic film in the recess by heating the substrate that has been subjected to the predetermined process to depolymerize the organic film. The amine and the isocyanate have a terminal bifunctional linear chain structure having two functional groups at both ends of a linear chain. At least one of the amine or the isocyanate has side chains connected to the linear chain contained in the linear chain structure.

A semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate, a gate dielectric, a gate electrode and dielectric structures. The gate dielectric has a top surface aligned with a top surface of the substrate. The gate electrode is disposed over the substrate and overlaps the gate dielectric. The gate electrode has first segments extending in parallel along a direction. The dielectric structures are disposed over the substrate, overlap the gate dielectric and extend in parallel along the direction. The dielectric structures and the first segments are arranged in an alternating pattern.

A structure for a FinFET, a FinFET and an LDMOS device are disclosed. The structures include a trench isolation adjacent a semiconductor fin and configured to increase a height of the semiconductor fin without increasing the footprint. The fin has junction and gate regions, and the trench isolation is adjacent a lower region the fin. The FinFET includes a first recess in the trench isolation adjacent the gate region of the fin, and a second recess in the trench isolation adjacent the junction region of the fin. The first recess is at least partially filled with a high dielectric constant (high-K) layer and a gate metal, and the second recess is at least partially filled with a low dielectric constant (low-K) layer. The trench isolation includes an upper portion and a lower portion that include materials of different compositions, e.g., a dopant in the upper portion.

A semiconductor package according to some example embodiments may include a chip base including a main chip region and an edge region around the main chip region, a device layer on the chip base, a wiring layer on the device layer, an upper insulating stack on the wiring layer, and a trench on the edge region, the trench recessed from the upper insulating stack to the device layer, and an inner surface of the trench exposed to an outside of the semiconductor chip.

An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.