A method of forming backside contacts to source/drain (S/D) regions of a semiconductor structure includes removing a substrate selectively to shallow trench isolations (STIs) and the extension regions to form first recesses between the STIs, filling the first recesses with first dielectric material, forming second recesses aligned to the S/D regions through the first dielectric material, and forming backside contacts to the extension regions within the second recesses.

An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

An integrated circuit device includes: a first fin-type active region and a second fin-type active region that extend on a substrate in a straight line in a first horizontal direction and are adjacent to each other in the first horizontal direction; a fin isolation region arranged between the first fin-type active region and the second fin-type active region on the substrate and including a fin isolation insulation structure extending in a second horizontal direction perpendicular to the first horizontal direction; and a plurality of gate lines extending on the first fin-type active region in the second horizontal direction, wherein a first gate line that is closest to the fin isolation region from among the plurality of gate lines is inclined to be closer to a center of the fin isolation region in the first horizontal direction from a lowermost surface to an uppermost surface of the first gate line.

A method for making a semiconductor device includes forming a first fin structure, a second fin structure, and a third fin structure over a substrate. The first through third fin structures all extend along a first lateral direction, and the second fin structure is disposed between the first and third fin structures. The method includes forming a mold by filling up trenches between neighboring ones of the first through third fin structures with a first dielectric material. The method includes cutting the second fin structure by removing an upper portion of the second fin structure. The method includes replacing the upper portion of the second fin structure with a second dielectric material to form a dielectric cut structure. The method includes recessing the mold to expose upper portions of the first fin structure and the third fin structure, respectively.

Fabrication method for a SiC integrated circuit which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.

A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

The gate electrode of a transistor includes at least one region with a p-type work function and at least one region with an n-type work function. The regions are located over corners formed between isolation regions and an active region. The double hump effect is reduced, which provides higher operational frequencies.

A semiconductor device includes a backside contact, a shallow trench isolation (STI), and a backside dielectric trench isolation (BDTI) below the STI. A top surface of the BDTI is connected to the STI on a backside of a high voltage region of the semiconductor device, a bottom surface of the BDTI is connected to a backside power interconnect, and the BDTI isolates a backside contact from a substrate.

A semiconductor device includes a shallow trench isolation (STI), a first doped region under the STI, an N-well region connected to the first doped region and the STI on a first side, a P-well region connected to the first doped region and the STI on a second side, a backside contact. A dopant concentration of the first doped region is higher than the dopant concentration of the N-well region and the dopant concentration of the P-well region.