The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture and operation. The structure includes: a semiconductor on insulator substrate; an insulator layer under the semiconductor on the insulator substrate; a handle substrate under insulator layer; a first well of a first dopant type in the handle substrate; a second well of a second dopant type in the handle substrate, adjacent to the first well; and a back-gate diode at a juncture of the first well and the second well.

A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.

A semiconductor device is provided. The semiconductor device includes a first field effect transistor (FET) region, a second FET region and a backside signal distribution network (BSSDN). The first FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends through the STI and the ILD. The second FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends to the STI. The BSSDN is disposed on the ILD in the first and second regions to contact with the contact in the first FET region.

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a passive device area and a logic device area on a substrate; forming a diffusion break between the passive device area and the logic device area, wherein the diffusion break extends into the substrate; removing a portion of the substrate to expose a bottom portion of the diffusion break; covering a first portion of the substrate underneath the passive device area and the bottom portion of the diffusion break with a hard mask; selectively removing a second portion of the substrate to expose at least a portion of a bottom surface of the logic device area; and depositing a backside interlevel dielectric (BILD) layer to cover the portion of the bottom surface of the logic device area. The semiconductor structure formed thereby is also provided.

A method of processing a substrate having a gap includes loading the substrate onto a substrate support unit, supplying an oligomeric silicon precursor and a nitrogen-containing gas to the substrate through a gas supply unit on the substrate support unit, and generating a direct plasma in a reaction space by applying a voltage to at least one of the substrate support unit and the gas supply unit, wherein a plurality of sub-steps are performed during the supplying of the oligomeric silicon precursor and the nitrogen-containing gas and the generating a direct plasma, and different plasma duty ratios are applied during the plurality of sub-steps.

A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.

A manufacturing method of a semiconductor device includes: forming a fin structure; forming a shallow trench isolation structure on the substrate of the fin structure; forming a dummy dielectric layer extending along sidewalls of nanostructures of the fin structure; forming a cladding layer conformally on the dummy dielectric layer; forming a dummy gate layer on the cladding layer; removing a portion of the dummy gate layer by performing an etching process, wherein an etch rate of the cladding layer is higher than an etch rate of the dummy gate layer; forming a gate spacer on the nanostructures of the fin structure, the dummy gate, the cladding layer and the dummy dielectric layer; forming two epitaxial structures coupled to the fin structure; and removing the cladding layer and the dummy dielectric layer before forming a gate metal layer engaging the semiconductor channel layers and located between the two epitaxial structures.

The present disclosure relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device, according to one embodiment, may comprise a gap-fill step of burying a gap-fill oxide in trenches formed on a substrate, so as to form a gap-fill oxide film. In one embodiment, the gap-fill step can comprise a high pressure oxidation (HPO) step. According to embodiments, a semiconductor device with electrical properties superior to those of a conventional semiconductor device can be manufactured.

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.