The invention provides a semiconductor structure, the semiconductor structure includes a substrate, two shallow trench isolation structures are located in the substrate, a first region, a second region and a third region are defined between the two shallow trench isolation structures, the second region is located between the first region and the third region. Two thick oxide layers are respectively located in the first region and the third region and directly contact the two shallow trench isolation structures respectively, and a thin oxide layer is located in the second region, the thickness of the thick oxide layer in the first region is greater than that of the thin oxide layer in the second region.

Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.

A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.

Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.

A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming first fin structures and a second fin structures over a substrate, forming a first gate stack and a second gate stack that extend in a first direction across the first fin structures and the second fin structures, respectively, and etching the first gate stack and the second gate stack to form a first trench through the first gate stack and a second trench through the second gate stack. A first dimension of the first trench in the first direction is greater than a second dimension of the second trench in the first direction. The method further includes forming a first gate cutting structure and a second gate cutting structure in the first trench and the second trench, respectively.

The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

The present application discloses a method for manufacturing a NAND flash, comprising: step 1, sequentially form a floating gate dielectric layer and a first polysilicon layer; step 2, sequentially forming an inter-gate dielectric layer and a second polysilicon layer, wherein a first doping concentration of the second polysilicon layer is less than a target doping concentration; step 3, forming a pattern transfer mask layer; step 4, patterning the pattern transfer mask layer; step 5, performing gate etching, wherein the first and second polysilicon layers subjected to the gate etching respectively form a polysilicon floating gate and the polysilicon control gate; step 6, forming a first spacer, wherein the first spacer in a storage area fully fills a first interval area; and step 7, performing self-aligned ion implantation to increase a doping concentration of the polysilicon control gate to the target doping concentration.

A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.

A chip includes one or more first channels extending in a first direction, a first epitaxial (epi) layer coupled to the one or more first channels, a first gate, wherein the one or more first channels pass through the first gate, one or more second channels extending in the first direction, a second epi layer coupled to the one or more second channels, and a second gate, wherein the one or more second channels pass through the second gate. The chip also includes a dielectric wall extending in the first direction, wherein the dielectric wall is disposed between the first epi layer and the second epi layer, and the dielectric wall is disposed between the first gate and the second gate. The chip further includes a backside bridge underneath the first gate and the second gate, wherein the backside bridge couples the first gate and the second gate.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.