A method of manufacturing a semiconductor device having a combination structure of a horizontal oxide layer structure and a vertical oxide layer structure, can include: etching from an upper surface of the semiconductor substrate to inside of the semiconductor substrate to form a trench; depositing oxides in the trench to form the vertical oxide layer structure; etching the vertical oxide layer structure from an upper surface thereof to decrease height of the vertical oxide layer structure, and to make a top surface of the vertical oxide layer structure be below the upper surface of the semiconductor substrate, in order to expose side surfaces of the trench; and forming, by an oxidation process, the horizontal oxide layer structure to cover part of the upper surface of the semiconductor substrate and the upper surface of the vertical oxide layer structure.

A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.

A semiconductor device manufacturing method includes: forming an organic film composed of a polymer having a urea bond in a recess by supplying amine and isocyanate to a surface of a substrate having the recess; performing a predetermined process on the substrate on which the organic film is formed in the recess; and removing the organic film in the recess by heating the substrate that has been subjected to the predetermined process to depolymerize the organic film. The amine and the isocyanate have a terminal bifunctional linear chain structure having two functional groups at both ends of a linear chain. At least one of the amine or the isocyanate has side chains connected to the linear chain contained in the linear chain structure.

A semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate, a gate dielectric, a gate electrode and dielectric structures. The gate dielectric has a top surface aligned with a top surface of the substrate. The gate electrode is disposed over the substrate and overlaps the gate dielectric. The gate electrode has first segments extending in parallel along a direction. The dielectric structures are disposed over the substrate, overlap the gate dielectric and extend in parallel along the direction. The dielectric structures and the first segments are arranged in an alternating pattern.

A semiconductor structure is disclosed that includes: a source feature and a drain feature disposed in a substrate; a gate structure disposed above the substrate and between the source feature and the drain feature; and a first ladder shallow trench isolation (STI) feature disposed in the substrate at least partially under the gate structure in a channel region between the source feature and the drain feature, the first ladder STI feature including a plurality of sections of different depths including a first depth section and a second depth section.

A method includes forming a dummy gate stack on a first protruding structure of a wafer, wherein the first protruding structure comprises a first semiconductor layer, etching the dummy gate stack to form a trench in the dummy gate stack and to reveal the first semiconductor layer, and removing the first semiconductor layer and a semiconductor strip underlying the first semiconductor layer to extend the trench downwardly. The trench is filled with a dielectric material to form a dielectric isolation region. A backside grinding process is performed on a semiconductor substrate of the wafer. The dielectric isolation region is revealed from a backside of the wafer. A backside dielectric layer is formed. on the backside of the wafer, and the backside dielectric layer contacts the dielectric isolation region.

A structure for a FinFET, a FinFET and an LDMOS device are disclosed. The structures include a trench isolation adjacent a semiconductor fin and configured to increase a height of the semiconductor fin without increasing the footprint. The fin has junction and gate regions, and the trench isolation is adjacent a lower region the fin. The FinFET includes a first recess in the trench isolation adjacent the gate region of the fin, and a second recess in the trench isolation adjacent the junction region of the fin. The first recess is at least partially filled with a high dielectric constant (high-K) layer and a gate metal, and the second recess is at least partially filled with a low dielectric constant (low-K) layer. The trench isolation includes an upper portion and a lower portion that include materials of different compositions, e.g., a dopant in the upper portion.

A method for forming a semiconductor device structure includes forming fin base structures over a first region and a second region of a substrate and channel layers over the fin base structures. The distances between the fin structures in the first region and the second region are different. The method also includes filling an isolation material between the fin base structures and recessing the isolation material to form a first isolation structure in the first region and a second isolation structure in the second region. The method also includes depositing a hard mask layer over the first isolation structure and the second isolation structure. The thicknesses of the hard mask layer in the first region and the second region are different, and the top surfaces of the hard mask layer in the first region and the second region are substantially at the same level.