A semiconductor device includes a first die, a second die, a first redistribution layer (RDL) structure and a connector. The RDL structure is disposed between the first die and the second die and is electrically connected to the first die and the second die and includes a first polymer layer, a second polymer layer, a first conductive pattern and an adhesion promoter layer. The adhesion promoter layer is between and in direct contact with the second polymer layer and the first conductive pattern. The connector is disposed in the first polymer layer and in direct contact with the second die and the first conductive pattern.

A method for semiconductor manufacturing includes removing an oxide layer disposed over a conductive feature, flowing a gallium precursor over the conductive feature, and depositing a metal over the conductive feature after flowing the gallium precursor. The conductive feature is adjacent to a dielectric feature. The metal is deposited selectively over the conductive feature relative to the dielectric feature.

A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

An MLG (multilayer graphene) device layer structure is connected with a via. The structure includes an M1 MLG interconnect device layer upon a dielectric layer. Interlayer dielectric isolates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is upon the interlayer dielectric. A metal via penetrates through the M2 MLG interconnect device layer, the interlayer dielectric and the M1 MLG interconnect device layer and makes edge contact throughout the thickness of both M1 MLG and M2 MLG layers. A method diffuses carbon from a solid phase graphene precursor through a catalyst layer to deposit MLG on a dielectric or metal layer via application of mechanical pressure at a diffusion temperature to form MLG layers.

Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.

A method of manufacturing the package structure includes providing a carrier on which first dies and second dies are respectively bonded to form stacks and an encapsulant laterally encapsulating the stacks, forming a dielectric layer over the stacks, forming openings in the dielectric layer to expose a portion of the second dies, forming trenches in the gaps through the encapsulant to expose the carrier, forming a cover layer on sidewalls of the trenches and sidewalls of the openings, and conformally forming a seed layer on the trenches, the openings, the carrier, the cover layer, the encapsulant, and the dielectric layer, forming a mask layer to cover a portion of the seed layer and expose the seed layer in the openings, and performing a plating process to form a conductive portion in the openings using the seed layer.

A selective deposition method is disclosed. The selective deposition method comprises providing a plurality of substrates in a process chamber, the plurality of substrates having a first surface comprising a first material and a second surface comprising a second material, the first surface being different than the second surface, and selectively forming a layer comprising a metal on the first surface relative to the second surface, wherein selectively forming the layer comprises: i) contacting the plurality of substrates with a precursor comprising a compound of the form MXnOm, wherein: M is a metal; X is selected from the group consisting of F, Cl, Br, and I; n and m are integers; n+2m is at least 4 to at most 6; and ii) contacting the plurality of substrates with a reactant, wherein step i) comprises pulsing the precursor for a pulse duration of greater than 10 seconds.

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of center studs disposed within cavity walls of a plurality of cavities in a top plate. The center studs and the cavity walls are oriented orthogonal to a first metal layer and extend through a first via layer and a second metal layer. Each center stud includes a metal layer stud in the second metal layer stacked on a via layer stud in the first via layer. A dielectric layer is disposed between the center studs and the cavity walls of the plurality of cavities in the top plate. The center studs are coupled to a first electrode, and the top plate is coupled to a second electrode in the interconnect layers. In some examples, the center studs can form vertically oriented cylindrical capacitive elements positioned for high capacitance density.