An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillars that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillars are conductive wires. A package body encapsulates the electronic component and the conductive pillars. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive pillars. In one embodiment, the electrical connection is made through the package body. In another embodiment, the electrical connection is made through the substrate.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

A light emitting module including a module substrate and a plurality of element structure bodies disposed on the module substrate. Each element structure body of the plurality of element structure bodies includes a submount substrate, a light emitting element disposed on the submount substrate, a light transmitting member disposed on the light emitting element, and a first cover member covering a lateral face of the light emitting element on the submount substrate. The light emitting module further includes a second cover member covering lateral faces of adjacent element structure bodies of the plurality of element structure bodies. A distance between submount substrates of the adjacent element structure bodies ranges from 0.05 mm to 0.2 mm.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.

A method of forming a package structure includes disposing a die adhesive layer on a wafer, lowering a partial connecting property of the die adhesive layer, separating a plurality of dies of the wafer and disposing each of the dies on a leadframe. A connecting property of a partial area of the die adhesive layer is lowered, and the connecting property of the partial area of the die adhesive layer is corresponding to a plurality of cutting streets of the wafer. The dies are separated according to the cutting streets of the wafer. The partial area of the die adhesive layer is corresponding to a plurality of leads of the leadframe, and a connecting strength between the die adhesive layer and each of the leads is lower than a connecting strength between the die adhesive layer and a die pad of the leadframe.

A semiconductor package comprises a base chip, a plurality of semiconductor chips sequentially stacked on the base chip, bump structures between the base chip and a lowermost semiconductor chip of the plurality of semiconductor chips, and between the plurality of semiconductor chips, adhesive layers surrounding the bump structures between the base chip and the lowermost semiconductor chip of the plurality of semiconductor chips and between the plurality of semiconductor chips. The adhesive layers have a width equal to or less than a width of each of the plurality of semiconductor chips in a direction parallel to an upper surface of the base chip. At least one of the adhesive layers comprises a polymer resin having a hydrophilic group, a photosensitive compound physically bonded to the polymer resin, and an ionic material crosslinking the polymer resin.

A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.