A package for a semiconductor device includes a metal base plate, a wall portion, a first metal film, and a lead portion. The base plate has a first region and a second region surrounding the first region. The wall portion has a first frame body comprising metal and a second frame body comprising resin. The first frame body is provided on the second region. The second frame body is provided on the first frame body. The first metal film is provided on the second frame body. The lead portion is conductively bonded to the first metal film. The first frame body is conductively bonded to the base plate. A thickness of the first frame body in a first direction that is a direction in which the first frame body and the second frame body are arranged is larger than a thickness of the first metal film in the first direction.

A method of manufacturing a display device includes forming a thin film transistor layer in an active area of a substrate, forming a metal layer on an edge area of the substrate, transferring first coating patterns to the edge area, the first coating patterns covering a portion of the metal layer corresponding to shapes of side surface lines, etching the metal layer to form the side surface lines, an upper surface of each of the side surface lines being covered by the first coating patterns, transferring a second coating pattern to the edge area, the second coating pattern covering a side surface of each of the side surface lines and the first coating patterns, and transferring light emitting elements to the thin film transistor layer. The second coating pattern includes openings corresponding to the first coating patterns in a plan view.

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter.

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

A semiconductor chip may include: a semiconductor substrate; a through silicon via that vertically penetrates the semiconductor substrate; an integrated device layer on a first surface of the semiconductor substrate and including integrated devices; a multi-wiring layer on the integrated device layer and including layers of wires; an upper metal layer on the multi-wiring layer and connected to the wires; and a lower metal layer on a second surface of the semiconductor substrate. The semiconductor substrate may include a lower bump area on the second surface of the semiconductor substrate, the lower bump area including bump pads thereon, and the lower metal layer may be on a periphery of the lower bump area.

A semiconductor structure includes a plurality of first wafers and a through-substrate via (TSV). The plurality of first wafers include a plurality of conductive connection lines. Each of the conductive connection lines is located in the corresponding first wafer. The through-substrate via passes through the plurality of first wafers and a plurality of end portions of the plurality of conductive connection lines. The plurality of end portions are embedded in the through-substrate via.

Various aspects of the present disclosure generally relate to integrated circuit devices, and to a conductive structure with multiple support pillars. A device includes a die including a contact pad. The device also includes a conductive structure. The conductive structure includes multiple support pillars coupled to the die, a bridge coupled to each of the multiple support pillars, and a cap pillar coupled to the bridge opposite the multiple support pillars. The device further includes a solder cap coupled to the cap pillar. The solder cap is electrically connected to the contact pad via the cap pillar, the bridge, and at least one of the multiple support pillars.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A light-emitting device includes a carrier substrate, a flip-chip light-emitting diode (LED) mounted onto the carrier substrate, and an electrode unit disposed between the carrier substrate and the flip-chip LED. The electrode unit includes first and second connecting electrodes that have opposite conductivity. Each of the first and second connecting electrodes includes an intermediate metal layer and a binding layer that are sequentially disposed on the flip-chip LED in such order. The binding layer includes a first portion being adjacent to the carrier substrate and forming an eutectic system with tin, and a second portion located between the first portion and the intermediate metal layer.

Aspects of the disclosure provide a semiconductor device and a method to fabricate the semiconductor device. The semiconductor device includes a first die comprising a first contact structure formed on a face side of the first die. The semiconductor device includes a first semiconductor structure and a first pad structure that are disposed on a back side of the first die. The first semiconductor structure is conductively connected with the first contact structure from the back side of the first die and the first pad structure is conductively coupled with the first semiconductor structure. An end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. The first die and a second die can be bonded face-to-face.