A bonding apparatus includes: a first holder configured to hold a first substrate; a second holder disposed to face the first holder and configured to hold a second substrate to be bonded to the first substrate; an imaging unit including a first portion including a first objective lens that captures an image of a first mark formed on the first substrate held by the first holder, and a second portion including a second objective lens that captures an image of a second mark formed on the second substrate held by the second holder; and a mover configured to relatively move the imaging unit, first holder, and second holder in a region between the first holder and the second holder. In the imaging unit, an optical axis of the first objective lens and an optical axis of the second objective lens are not on a same straight line.

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

A processing method including a step that takes an image of the end face of a reference substrate, whose warp amount is known, over the whole periphery thereof using a camera to obtain shape data of the end face of the reference substrate; a step that takes an image of the end face of a process substrate over the whole periphery thereof using a camera to obtain shape data of the end face of the process substrate; a step that calculates warp amount of the process substrate based on the obtained shape data; a step that forms a resist film on a surface of the process substrate; a step that determines the supply position from which an organic solvent is supplied to a peripheral portion of the resist film and dissolves the peripheral portion by the solvent supplied from the supply position to remove the same from the process substrate.

Determining a semiconductor device manufacturing parameter may include determining an EPM (electrical measurement parameters) group that has a correlation in a baseline EPM dataset including EPMs of a device manufactured under a baseline condition, deriving principal components (PCs) corresponding to main correlation axes between EPMs in the EPM group, deriving a PC-based dataset including a baseline PC dataset and a conditional split PC dataset by converting the baseline EPM dataset and a conditional split EPM dataset measured from devices manufactured under conditional splits into a PC domain, determining, using the PC-based dataset, respective PCs which are effectively changed by the conditional splits, obtaining split variation information of the conditional splits, extracting an optimal point capable of optimizing a figure of merit of a semiconductor device within a range of the PC-based dataset, and deriving information for process feedback for realizing the optimal point using the split variation information.

There is provided a configuration that includes: at least one transfer mechanism configured to transfer a substrate and at least one processing mechanism configured to process the substrate; an earthquake detector configured to detect an earthquake; and a controller configured to control the at least one transfer mechanism and the at least one processing mechanism according to a detection result of the earthquake detector, wherein the controller is configured to be capable of performing a stopping operation of the at least one transfer mechanism according to a P wave (initial tremor wave) and an S wave (principal fluctuation wave).

One example discloses a degradation circuit, including: a first structure configured to be coupled to an integrated circuit (IC); a second structure, coupled to the first structure, and configured to be coupled to the IC; wherein together the first and second structures form a degradation detection element; and a controller, coupled to the degradation detection element, and configured to set an operational state of the IC based on the degradation detection element.

A substrate inspection method includes radiating light onto a substrate, extracting a spectrum representing an intensity of light according to a wavelength from a light reflected from the substrate, analyzing the extracted spectrum in units of each of an entire substrate, a shot, a chip, and a block, generating a spectrum distribution map indicating reflectivity for each wavelength band by using the analyzed spectrum, and extracting a weak point in the substrate based on the spectrum distribution map.

A defect density calculation method according to one embodiment of the present disclosure is a method of calculating a temporal change of the defect density distribution in a semiconductor layer. The method includes calculating the temporal change of the defect density distribution on the basis of an arithmetic function using at least the activation energy of a detect included in the semiconductor layer, the processing temperature of the semiconductor layer, and the processing time of the semiconductor layer as arguments.

Described herein is a technique capable of uniformizing a quality of a film even when a processing environment changes. According to one aspect thereof, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate into a process chamber; (b) supplying a gas to the substrate in the process chamber through a dispersion plate of a shower head while heating the dispersion plate by a shower head heater and exhausting the gas; (c) unloading the substrate; (d) measuring a temperature of the shower head before loading a subsequent substrate; and (e) comparing the temperature of the shower head after (d) with a pre-set temperature, and operating the shower head heater to control the temperature of the shower head to become close to the pre-set temperature when a difference between the temperature of the shower head and the pre-set temperature is greater than a predetermined value.

The application provides a display panel motherboard and manufacturing method thereof. The display panel motherboard includes display panel forming areas distributed in an array and a test area adjacent to the display panel forming areas. The display panel motherboard includes an array mother substrate; a light-emitting layer, disposed on a surface of a side of the array mother substrate and located in the display panel forming areas; and a test component, disposed on the surface of the array mother substrate and located in the test area, the test component including a test block including a fluorescent layer, disposed on the surface of the array mother substrate and emitting light upon being irradiated by activation light; a target test layer, disposed on the side of the fluorescent layer facing away from the surface; and a positioning reference portion, disposed at a peripheral side of the target test layer.