A semiconductor-on-insulator (SOI) structure includes a semiconductor layer over a buried oxide over a handle wafer. A carbon-doped epitaxial layer is in the semiconductor layer. A doped body region is in the semiconductor layer under the carbon-doped epitaxial layer and extending to the buried oxide. The carbon-doped epitaxial layer and the doped body region have a same conductivity type. Alternatively, a doped body region in the semiconductor layer and extending to the buried oxide includes carbon dopants and body dopants, wherein a peak carbon dopant concentration is situated at a first depth, and a peak body dopant concentration is situated at a second depth below the first depth. Alternatively, an SOI transistor in the semiconductor layer includes a halo region having a different conductivity type from a source and a drain. The halo region includes carbon dopants and body dopants. The source and/or the drain adjoin the halo region.

A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer has a higher germanium concentration than the second semiconductor layer; forming a semiconductor cap over the second semiconductor layer; forming a first bonding layer over the semiconductor cap; bonding the first boding layer to a second bonding layer over a carrier substrate to form a bonded structure; and performing a wafer splitting process to split the first semiconductor layer into a first portion and a second portion separated from each other, such that the first portion of the first semiconductor layer and the substrate are removed from the bonded structure.

An integrated device comprising a buried oxide layer within a trench within a top surface of a substrate. A silicon layer formed over the buried oxide layer and the top surface of the substrate.

A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

A method for transferring a semiconductor layer from a donor substrate having a weakening plane to a receiver substrate having comprising a bonding face that has open cavities includes putting the donor substrate and the bonding face of the receiver substrate in contact, producing an assembly wherein the cavities are buried, and separating the assembly by fracture along the weakening plane. The bonding face of the receiver substrate includes, apart from the open cavities, a bonding surface that comes into contact with the donor substrate when the assembly is produced. The bonding surface includes a region devoid of cavities one dimension of which is at least 100 m and which has a surface area of at least 1 mm.sup.2, and an intercavity space that occupies from 15 to 50% of the bonding face of the receiver substrate.

A manufacturing method for a semiconductor structure includes: providing a Si-supporting substrate having a SiO.sub.2 protection layer on a surface of the Si-supporting substrate; thinning the SiO.sub.2 protection layer to form a SiO.sub.2 intermediate layer; disposing a Si growth substrate on a side, away from the Si-supporting substrate, of the SiO.sub.2 intermediate layer; and disposing a device layer on a side, away from the Si-supporting substrate, of the Si growth substrate. The technical solutions of the present disclosure may reduce a possibility of generating parasitic capacitance and leakage current, and greatly improve the reliability of a device.

A method of preparing a semiconductor-on-insulator structure from a bonded structure including a handle substrate, a donor substrate including a cleave plane, and a dielectric layer positioned between the handle substrate and the donor substrate, the method includes cleaving the bonded structure at the cleave plane to form a cleaved structure including the handle substrate, the dielectric layer, and a device layer. The single crystal semiconductor device layer defines a damaged region at an exposed surface opposite the dielectric layer. The damaged region includes single crystal semiconductor material and extends a thickness from the exposed surface. The method also includes removing the damaged region from the cleaved structure using a clean-and-etch operation that includes contacting the exposed surface of the device layer with an alkaline solution at a temperature and for a duration sufficient to remove the damaged region and smoothing the device layer with the damaged region removed.

A process for fabricating a semiconductor or piezoelectric structure comprises the following successive steps: (a) providing a donor substrate comprising a piezoelectric or semiconductor layer, (b) providing a receiver substrate, (c) treating a free surface of the donor substrate and/or a free surface of the receiver substrate, (d) bonding the donor substrate to the receiver substrate, the at least one treated free surface being at the interface between the donor substrate and the receiver substrate, and (e) transferring a portion of the piezoelectric or semiconductor layer from the donor substrate to the receiver substrate. The treatment of the free surface of the donor substrate and/or of the free surface of the receiver substrate comprises the following successive steps: (c1) chemical-mechanical polishing, and (c2) removing material from a peripheral region of the polished surface.

Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.