A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, a source region and a drain region, and a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.

Cleaving systems and methods for cleaving a semiconductor structure. The systems and methods may involve a combination of thermally and mechanically induced stress. The cleave system may include a vacuum chuck which deflects the semiconductor structure and a heater which heats the structure while the vacuum is applied. The combination of thermal and mechanical stress causes the structure to cleave along a cleave plane.

The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.

The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 .Math.cm and 30 k.Math.cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.

The present disclosure generally relates to semiconductor processing including facet suppression for an epitaxial growth process. In an example, a semiconductor device includes a first semiconductor material, a dielectric layer, and a second semiconductor material. The first semiconductor material includes a monocrystalline surface. The dielectric layer is over the first semiconductor material and has an opening to the first semiconductor material. The opening is defined at least in part by a sidewall of the dielectric layer. The sidewall includes a retrograde sidewall portion. The retrograde sidewall portion is planar and retrograde laterally into the dielectric layer from a distance distal from an interface between the dielectric layer and the monocrystalline surface of the first semiconductor material to a surface of the dielectric layer at the interface. The second semiconductor material is over the first semiconductor material. The second semiconductor material is at least partially in the opening.

Fully-depleted silicon-on-insulator structures and methods for preparing fully-depleted silicon-on-insulator structures. The fully-depleted silicon-on-insulator structure may include a top layer, a handle structure and a dielectric layer disposed between the silicon top layer and handle structure. The dielectric layer of the silicon-on-insulator structure may be composed of hafnia, zirconia, alumina, or combinations thereof. In some embodiments, the dielectric layer is relatively thick such as at least 20 nm or even at least 50 nm.

A composite substrate includes a substrate, a high-resistance layer located on the substrate, the high-resistance layer comprising a first low-temperature aluminum nitride (AlN) layer, a high-temperature AlN layer and a second low-temperature AlN layer which are stacked in sequence, and a growth substrate located on a side, away from the substrate, of the high-resistance layer. Under the action of the first low-temperature AlN layer, a tensile stress on the high-temperature AlN layer may be reduced, to reduce a dislocation, and further improve a crystal quality of the high-temperature AlN layer and ensure resistivity of the high-temperature AlN layer; and an element of Al in the high-temperature AlN layer is prevented from diffusing into the growth substrate, to protect the crystal quality of the high-temperature AlN layer and improve a bonding effect between the high-resistance layer and the growth substrate. Thus, stability and reliability of the composite substrate are greatly improved.

An isolator includes a substrate; a first insulating film on the substrate; a second insulating film on the first insulating film, a third insulating film on the second insulating film, a first interconnect in the second insulating film, and first and second coils. The first interconnect has a thickness equal to a film thickness of the second insulating film. The first coil extends in the first and second insulating films. The first coil has a length in the extending direction greater than the thickness of the first interconnect. The third insulating film is provided on the second insulating film, and covers the first interconnect and the first coil. The second coil is provided on the third insulating film, and faces the first coil via the third insulating film.

A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.