SEMICONDUCTOR STRUCTURE FOR DIGITAL AND RADIOFREQUENCY APPLICATIONS, AND METHOD FOR MANUFACTURING SUCH A STRUCTURE

Abstract

The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 .Math.cm and 30 k.Math.cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.

Claims

1. A semiconductor-on-insulator multilayer structure comprising: a semiconductor carrier substrate; a first electrically insulating layer positioned over the semiconductor carrier substrate; an intermediate layer positioned on the first electrically insulating layer; a second electrically insulating layer positioned on the intermediate layer; an active semiconductor layer positioned on the second electrically insulating layer; a digital component on the active semiconductor layer, in which a portion of the intermediate layer below the digital component is a semiconductor layer, and a radio frequency component on the active semiconductor layer, in which a portion of the intermediate layer below the radio frequency component is a third electrically insulating layer.

2. The structure of claim 1, wherein the digital component is adjacent to the digital component on the active semiconductor layer.

3. The structure of claim 2, wherein the second electrically insulating layer has a thickness small than a thickness of the first electrically insulating layer.

4. The structure of claim 3, wherein the first electrically insulating layer has a thickness between 20 nm and 1000 nm and the second electrically insulating layer has a thickness between 10 nm and 100 nm.

5. The structure of claim 3, wherein a sum of thicknesses of the first electrically insulating layer, the second electrically insulating layer, and the third electrically insulating layer is between 50 nm and 1500 nm.

6. The structure of claim 2, further comprising a charge-trapping layer between the semiconductor carrier substrate and the first electrically insulating layer.

7. The structure of claim 6, wherein the charge-trapping layer comprises polysilicon or porous silicon.

8. The structure of claim 6, wherein the charge-trapping layer is configured to accumulate electrical charge under first electrically insulating layer.

9. The structure of claim 2, wherein the intermediate first semiconductor layer comprises crystalline or polycrystalline material.

10. The structure of claim 2, wherein the intermediate first semiconductor layer comprises amorphous material.

11. The structure of claim 2, wherein the first electrically insulating layer comprises a layer of oxide.

12. The structure of claim 2, wherein the second electrically insulating layer comprises a layer of oxide.

13. The structure of claim 2, wherein the third electrically insulating layer comprises a layer of oxide.

14. The structure of claim 2, wherein the active semiconductor layer has a thickness between 3 nm and 30 nm.

15. The structure of claim 2, wherein the active semiconductor layer has a thickness between 5 nm and 20 nm.

16. The structure of claim 2, comprising a trench that extends from that extends from a top surface of the active semiconductor layer through the second electrically insulating layer and the intermediate layer down to the first electrically insulating layer.

17. The structure of claim 16, comprising a lateral cavity formed in the intermediate layer.

18. The structure of claim 17, comprising third electrically insulating layer deposited into the lateral cavity.

19. The structure of claim 18, comprising a second radio frequency component positioned on the active semiconductor layer.

20. The structure of claim 19, wherein the second radio frequency component is positioned above the third electrically insulating layer deposited into the lateral cavity.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Other advantages and features of the present disclosure will become apparent upon reading the following description given by way of illustrative and non-limiting example, with reference to the following accompanying figures:

[0077] FIG. 1 is a schematic of one embodiment of a multilayer structure according to present disclosure, comprising two FD-SOI regions and one RF-SOI region;

[0078] FIG. 2 is a schematic of one of the FD-SOI regions of the structure illustrated in FIG. 1;

[0079] FIG. 3 is a schematic of the RF-SOI region of the structure illustrated in FIG. 1;

[0080] FIG. 4 is a schematic of an intermediate structure, comprising an intermediate first semiconductor layer on a carrier substrate that has been covered beforehand with a first electrically insulating layer;

[0081] FIG. 5 is a schematic of the intermediate structure of FIG. 4, in which a cavity has been produced;

[0082] FIG. 6 is a schematic of the intermediate structure of FIG. 5, in which a cavity has been filled with an electrically insulating layer;

[0083] FIG. 7 is a schematic of a multilayer structure;

[0084] FIG. 8 is a schematic of the multilayer structure of FIG. 7, in which a trench has been produced;

[0085] FIG. 9 is a schematic of the multilayer structure of FIG. 8, in which a lateral cavity has been produced;

[0086] FIG. 10 is a schematic of the multilayer structure of FIG. 9, in which the cavity has been filled with an electrically insulating layer.

DETAILED DESCRIPTION

[0087] A first subject of the present disclosure relates to a semiconductor-on-insulator multilayer structure that is usable both for digital applications and for radiofrequency applications.

[0088] FIG. 1 illustrates one embodiment of such a multilayer structure 1 according to the present disclosure.

[0089] With reference to FIG. 1, the multilayer structure 1 comprises in succession, from a back side to a front side of the structure, a semiconductor carrier substrate 2, a first electrically insulating layer 3, an intermediate layer I, a second electrically insulating layer 5, and an active semiconductor layer 6.

[0090] The semiconductor carrier substrate 2 is a highly resistive substrate, i.e., it has an electrical resistivity between 500 .Math.cm and 30 k.Math.cm, and preferably between 1 k.Math.cm and 10 k.Math.cm. A high resistivity gives the carrier substrate the ability to limit electrical losses and to improve the radiofrequency performance of the structure.

[0091] The first electrically insulating layer 3 allows the carrier substrate 2 to be insulated from the intermediate layer I and from the layers superjacent the intermediate layer.

[0092] The first electrically insulating layer 3 is preferably a layer of oxide. Since this layer is buried in the structure between the carrier substrate and the intermediate layer, it may also be called the first BOX. It is preferably a layer of silicon oxide.

[0093] The thickness of the first electrically insulating layer 3 is relatively large, and preferably between 20 nm (nanometers) and 1000 nm. Specifically, too small a thickness, in particular, one smaller than 20 nm, would run the risk of breakdown of the first electrically insulating layer. In particular, the first electrically insulating layer 3 preferably has a thickness larger than that of the active semiconductor layer 6.

[0094] Optionally, the multilayer structure 1 also comprises a charge-trapping layer 8, which is preferably made of polysilicon or of porous silicon, arranged between the carrier substrate 2 and the first electrically insulating layer 3. This charge-trapping layer allows the electrical charge that accumulates under the first electrically insulating layer 3 to be trapped.

[0095] The second electrically insulating layer 5 allows the active semiconductor layer 6 to be insulated from the intermediate layer I and from the layers subjacent the intermediate layer.

[0096] The second electrically insulating layer 5 is preferably a layer of oxide, and preferably a layer of silicon oxide. Since this layer is buried in the structure between the intermediate layer and the active semiconductor layer, it may be called the second BOX.

[0097] The second electrically insulating layer 5 has a thickness that is relatively small, and smaller than that of the first electrically insulating layer 3. This small thickness makes it possible to be able to control the threshold voltage of the transistor via suitable biasing (back bias voltage) of the subjacent intermediate layer. A thickness of the second electrically insulating layer 5 is preferably between 10 nm and 100 nm for this reason.

[0098] The active semiconductor layer 6 is intended for the production both of digital components 11 and optionally of radiofrequency components 12, the components produced depending on the digital and radiofrequency applications desired for the structure.

[0099] The active semiconductor layer 6 is preferably a layer of single-crystal silicon.

[0100] The thickness of the active semiconductor layer 6 is preferably between 3 nm and 30 nm, and more preferably between 5 nm and 20 nm. It is preferable for the thickness of the active semiconductor layer to be uniform over all the extent of the material, i.e., for its thickness to vary by 1 nm or less, in order to optimize the operation of the FD-SOI regions, in a fully depleted mode. The FD-SOI regions are described in detail below in the present text.

[0101] The multilayer structure 1 comprises a plurality of regions intended for different applications, including at least one FD-SOI region for digital applications and at least one RF-SOI region for radiofrequency applications.

[0102] In order to be able to combine an FD-SOI region and an RF-SOI region in one and the same structure, the intermediate layer I is arranged between the first and second electrically insulating layers 3, 5, and the nature of this intermediate layer I is different depending on whether it is in an FD-SOI region or in an RF-SOI region.

[0103] One of the two FD-SOI regions of the structure of FIG. 1 is shown in FIG. 2.

[0104] In an FD-SOI region, the intermediate layer I is an intermediate first semiconductor layer 4.

[0105] The intermediate first semiconductor layer 4 is advantageously made of a crystalline material or of an amorphous material, which may optionally be doped. This material is chosen so that the semiconductor layer may be biased in order to control the threshold voltage of the transistor.

[0106] The material of the intermediate first semiconductor layer 4 is advantageously a semiconductor preferably chosen from: single-crystal silicon, polysilicon, and an alloy of Si and Ge.

[0107] The FD-SOI region comprises at least one digital component 11 in the active semiconductor layer 6. In FIG. 1, the digital component is thus positioned plumb with the semiconductor layer.

[0108] The RF-SOI region of the structure of FIG. 1 is shown in FIG. 3.

[0109] In an RF-SOI region, the intermediate layer I is an electrically insulating layer 7, called the third electrically insulating layer.

[0110] The third electrically insulating layer 7 allows the active semiconductor layer 6 to be better isolated from the carrier substrate 2, i.e., the front gate to be electrically isolated from the back gate of the transistor.

[0111] The third electrically insulating layer 7 is preferably a layer of oxide. Since this layer is buried in the structure between the first and second electrically insulating layers, it may be called the third BOX. It is preferably a layer of silicon oxide.

[0112] The RF-SOI region comprises at least one radiofrequency component 12 plumb with the third electrically insulating layer 7, in particular, in the active semiconductor layer 6. The radiofrequency component 12 may also be formed in one of the electrically insulating layers 5, 7 or 3, and preferably on the second electrically insulating layer 5, in order to benefit from the effect of a BOX composed of three electrically insulating layers 5, 7 and 3. In FIG. 3, the radiofrequency component is thus positioned plumb with the third electrically insulating layer.

[0113] According to one preferred embodiment, the sum of the thicknesses of the first electrically insulating layer 3, of the second electrically insulating layer 5, and of the third electrically insulating layer 7 is between 50 nm and 1500 nm. The thickness of each of the three electrically insulating layers is therefore adjusted to obtain the described total thickness. Such a thickness allows the breakdown voltage to be optimized for the radiofrequency components.

[0114] Three embodiments of a process for fabricating a multilayer structure 1 such as described above will now be described.

[0115] According to a first embodiment, a first donor substrate is initially provided.

[0116] A weakened zone is formed in the substrate to delineate an intermediate first semiconductor layer. The weakened zone is formed in the donor substrate at a predefined depth that corresponds substantially to the thickness of the semiconductor layer to be transferred. Preferably, the weakened zone is created by implanting hydrogen and/or helium atoms into the donor substrate.

[0117] The intermediate first semiconductor layer is then transferred to a semiconductor carrier substrate, which is a receiver substrate, by bonding the donor substrate to the carrier substrate via the first electrically insulating layer then by detaching the donor substrate along the weakened zone (SMART CUT process).

[0118] Alternatively, the transfer may be achieved by thinning the donor substrate from the side thereof opposite the side bonded to the carrier substrate, until the thickness desired for the intermediate first semiconductor layer is obtained.

[0119] Optionally, before the bonding step, a charge-trapping layer is formed on the carrier substrate, between the carrier substrate and the first electrically insulating layer.

[0120] As illustrated in FIG. 4, an intermediate structure comprising the carrier substrate 2, the charge-trapping layer 8 when present, the first electrically insulating layer 3 and the transferred intermediate first semiconductor layer I is then obtained.

[0121] With reference to FIG. 5, one segment of the intermediate first semiconductor layer is then removed down to the first electrically insulating layer in order to form a cavity 9. In FIG. 5, the cavity 9 is bounded in the thickness of the structure by the first electrically insulating layer 3, and laterally by two segments of the intermediate first semiconductor layer 4.

[0122] The local removal may advantageously be carried out by etching. To this end, a lithography mask is deposited on the intermediate first semiconductor layer 4. The mask is provided with at least one aperture. The intermediate first semiconductor layer is then etched through the aperture of the mask in order to form the cavity 9. Any known etching technique suitable for this purpose may be used, such as, for example, dry etching.

[0123] With reference to FIG. 6, the third electrically insulating layer 7 is then deposited in the cavity 9, in order to fill the cavity. After this deposition, the upper surface of the third electrically insulating layer lies flush with the upper surface of the semiconductor layer.

[0124] Moreover, a second donor substrate is provided.

[0125] A weakened zone is formed in the substrate to delineate a second semiconductor layer 6. The weakened zone may be formed in the same way used to delineate the intermediate first semiconductor layer.

[0126] The second semiconductor layer 6 is then transferred to the intermediate structure, by bonding the second donor substrate to the intermediate structure via the second electrically insulating layer 5 (formed either on the intermediate structure or on the donor substrate) then by detaching the donor substrate along the weakened zone (SMART CUT process).

[0127] Alternatively, the transfer may be achieved by thinning the second donor substrate from the side thereof opposite the side bonded to the intermediate structure, until the thickness desired for the second semiconductor layer 6 is obtained.

[0128] Optionally, before the transferring step, it is possible to carry out a treatment of the free surfaces of the intermediate first semiconductor layer and of the third electrically insulating layer, in order to decrease the roughness thereof. This surface treatment improves the bonding of the second electrically insulating layer to the intermediate first semiconductor layer and third electrically insulating layer.

[0129] Next, one or more digital components 11 are produced on the second semiconductor layer 6, which is the active semiconductor layer. The digital components are produced plumb with the intermediate first semiconductor layer, i.e., facing the intermediate first semiconductor layer in the direction of the thickness of the structure. This allows an FD-SOI region to be obtained.

[0130] One or more radiofrequency components 12 are also produced on the active semiconductor layer, plumb with the third electrically insulating layer 7. This allows an RF-SOI region to be obtained.

[0131] The first embodiment that has just been described comprises two steps of delineating and transferring a semiconductor layer. This is most particularly advantageous in the case where the intermediate first semiconductor layer is crystalline. The transfer of such a layer from a donor substrate allows its crystal quality to be preserved on the final structure.

[0132] When an optimization of the crystal quality of the intermediate first semiconductor layer is not required, for example, when the latter is amorphous, it is possible to form the intermediate first semiconductor layer by deposition on the first electrically insulating layer. This process then employs only a single transferring step, i.e., the step of transferring the active semiconductor layer, and is therefore more economical.

[0133] This method corresponds to a second embodiment that will now be described.

[0134] According to a second embodiment, an intermediate structure, as illustrated in FIG. 4, is formed by depositing an intermediate first semiconductor layer 4 on a carrier substrate 2 covered beforehand with a first electrically insulating layer 3.

[0135] The intermediate first semiconductor layer 4 may be formed by epitaxy on the carrier substrate covered with a first electrically insulating layer, or, alternatively, deposited on the carrier substrate, in particular, by chemical vapor deposition (CVD).

[0136] Optionally, before the deposition of the intermediate first semiconductor layer, a charge-trapping layer 8 is formed on the carrier substrate 2, between the carrier substrate and the first electrically insulating layer 3.

[0137] With reference to FIG. 5, one segment of the intermediate first semiconductor layer 4 is then removed down to the first electrically insulating layer 3 in order to form a cavity 9. In FIG. 5, the cavity 9 is bounded in the thickness of the structure by the first electrically insulating layer 3, and laterally by two segments of the intermediate first semiconductor layer 4.

[0138] The local removal may advantageously be carried out by etching, similarly to the first embodiment.

[0139] With reference to FIG. 6, an electrically insulating layer 7, called the third electrically insulating layer, is then deposited in the cavity 9 in order to fill the cavity. After this deposition, the upper surface of the third electrically insulating layer 7 lies flush with the upper surface of the intermediate first semiconductor layer 4.

[0140] Moreover, a donor substrate is provided.

[0141] A weakened zone is formed in the substrate to delineate a second semiconductor layer 6. The weakened zone may be formed in the same way used for the first embodiment.

[0142] The second semiconductor layer 6 is then transferred to the intermediate structure, by bonding the donor substrate to the intermediate structure via the second electrically insulating layer 5 then by detaching the donor substrate along the weakened zone (SMART CUT process).

[0143] Alternatively, the transfer may be achieved by thinning the donor substrate from the side thereof opposite the side bonded to the intermediate structure, until the thickness desired for the second semiconductor layer 6 is obtained.

[0144] Optionally, before the transferring step, it is possible to carry out a treatment of the free surfaces of the intermediate first semiconductor layer 4 and of the third electrically insulating layer 7, in order to decrease the roughness thereof. This surface treatment improves the bonding of the second electrically insulating layer to the intermediate first semiconductor layer and third electrically insulating layer.

[0145] Next, one or more digital components 11 are produced on the second semiconductor layer 6, which is the active semiconductor layer. The digital components 11 are produced plumb with the intermediate first semiconductor layer 4. This allows an FD-SOI region to be obtained.

[0146] One or more radiofrequency components 12 are also produced on the active semiconductor layer, plumb with the third electrically insulating layer 7. This allows an RF-SOI region to be obtained.

[0147] According to a third embodiment, the fabricating process comprises the same steps as those of the first embodiment or those of the second embodiment. However, contrary to the latter embodiments, in which the local removal of a segment of the intermediate first semiconductor layer 4 and the deposition of the third electrically insulating layer 7 in the cavity 9 are carried out before the transfer of the second semiconductor layer 6 to the intermediate structure, the removing and depositing steps are carried out after the transferring step.

[0148] In particular, the removing and depositing steps according to the third embodiment could be carried out on a structure in which a third electrically insulating layer 7 has been formed beforehand, according to the first or second embodiment described above.

[0149] The removing and depositing steps of the third electrically insulating layer 7 may be carried out before the digital and radiofrequency components 11, 12 are produced, or indeed after the digital and radiofrequency components are produced, i.e., during the fabrication of the transistor. It may be, in particular, a question of MOS transistor, such as a CMOS transistor.

[0150] According to this third embodiment, with reference to FIGS. 7 and 8, a trench 10 is dug at a defined distance from the edge of the structure, so that the trench extends from the free surface of the active semiconductor layer 6, through the second electrically insulating layer 5 and the intermediate first semiconductor layer 4, down at least to the first electrically insulating layer 3. This allows the lateral segment delineated by the trench 10 to be physically isolated from the rest of the structure.

[0151] With reference to FIG. 9, the intermediate first semiconductor layer 4 in the lateral segment is then locally removed in order to form a cavity 9.

[0152] As shown in FIG. 9, the cavity 9 is a lateral cavity, located on the edge of the useful zone, and opens onto the exterior of the structure. It is bounded in the thickness of the structure by the first electrically insulating layer 3 and the second electrically insulating layer 5, and laterally by the one or more trenches 10.

[0153] With reference to FIG. 10, the third electrically insulating layer 7 is then deposited in the cavity 9, in order to fill the cavity.

[0154] One or more radiofrequency components 12 may then be produced on the active semiconductor layer 6, plumb with the third electrically insulating layer 7. An RF-SOI region is then obtained on the structure edge.

[0155] The advantage of producing the third electrically insulating layer during the process for fabricating the transistor is that it makes it possible to use the etch masks of this process, and therefore to benefit from an optimal alignment of the various layers of the structure.