A semiconductor-on-insulator (SOI) structure includes a semiconductor layer over a buried oxide over a handle wafer. A carbon-doped epitaxial layer is in the semiconductor layer. A doped body region is in the semiconductor layer under the carbon-doped epitaxial layer and extending to the buried oxide. The carbon-doped epitaxial layer and the doped body region have a same conductivity type. Alternatively, a doped body region in the semiconductor layer and extending to the buried oxide includes carbon dopants and body dopants, wherein a peak carbon dopant concentration is situated at a first depth, and a peak body dopant concentration is situated at a second depth below the first depth. Alternatively, an SOI transistor in the semiconductor layer includes a halo region having a different conductivity type from a source and a drain. The halo region includes carbon dopants and body dopants. The source and/or the drain adjoin the halo region.

An integrated device comprising a buried oxide layer within a trench within a top surface of a substrate. A silicon layer formed over the buried oxide layer and the top surface of the substrate.

A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

A semiconductor device includes a first buried layer and a second buried layer both have a first conductivity type and are disposed in a substrate, where the second buried layer is disposed on the first buried layer. A first well region has the first conductivity type and is disposed above the second buried layer. A second well region has a second conductivity type and is adjacent to the first well region. A deep trench isolation structure is disposed in the substrate and surrounds the first and second well regions, where the bottom surface of the deep trench isolation structure is lower than the bottom surface of the first buried layer. A source region is disposed in the second well region. A drain region is disposed in the first well region. A gate electrode is disposed on the first and second well regions.

An isolator includes a substrate; a first insulating film on the substrate; a second insulating film on the first insulating film, a third insulating film on the second insulating film, a first interconnect in the second insulating film, and first and second coils. The first interconnect has a thickness equal to a film thickness of the second insulating film. The first coil extends in the first and second insulating films. The first coil has a length in the extending direction greater than the thickness of the first interconnect. The third insulating film is provided on the second insulating film, and covers the first interconnect and the first coil. The second coil is provided on the third insulating film, and faces the first coil via the third insulating film.

A multi-time programable (MTP) memory cell is described. The MTP memory cell includes a buried oxide (BOX) layer. The MTP memory cell also includes a semiconductor-on-insulator (SOI) layer on the BOX layer. The MTP memory cell further includes a planar multi-gate structure. The planar multi-gate structure includes a pass-gate on the SOI layer. The planar multi-gate structure also includes a memory-gate.

A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).

A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Semiconductor wafers and methods of fabricating the same are provided. An example semiconductor wafer has multiple die regions separated by a die spacing region and includes a wafer substrate, multiple dies disposed over the wafer substrate, and multiple buried sacrificial structures corresponding to the multiple dies. Each die is located in the corresponding die region and further includes a die substrate, an integrated circuit (IC) device disposed in the die substrate, and a multi-layer interconnect structure disposed on the IC device. The buried sacrificial structure is surrounding the die substrate and disposed between the die and the wafer substrate. The buried sacrificial structure further includes a bottom portion disposed in the die region and a side portion circumferentially connected to the bottom portion. The side portion is located in the die spacing region surrounding the corresponding die and disposed on the sidewall of the die substrate.

An integrated circuit (IC) is described. The IC includes a substrate supporting a buried oxide (BOX) layer. The IC also includes a first-type semiconductor layer on the BOX layer. The IC further includes an oxide layer on the first-type semiconductor layer. The IC also includes a second-type semiconductor layer on the oxide layer, in which a perforated portion of the first-type semiconductor layer is exposed through an opening in the second-type semiconductor layer and the oxide layer. The IC further includes a contact between the first-type semiconductor layer and the second-type semiconductor layer. The IC also includes the BOX layer defining a cavity and partially in the substrate.