Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.

A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.

A process of forming an oxide layer, the oxide layer, a semiconductor device, and a method for manufacturing a semiconductor device. The process of forming the oxide layer including conducting atomic layer deposition at a temperature of less than about 400 C., wherein the atomic layer deposition includes: supplying a metal or semi-metal precursor and a first reaction catalyst to a substrate positioned in a chamber for atomic layer deposition to adsorb the metal or the semi-metal precursor on a surface of the substrate; and supplying a reactant and a second reaction catalyst to the substrate on which the metal or semi-metal precursor is adsorbed to form the oxide layer, wherein the first reaction catalyst and the second reaction catalyst comprise primary or secondary amine, respectively.

A method for manufacturing a semiconductor device according to an embodiment has a first film formation step, a second film formation step, and an oxidizing step. In the first film formation step, a first coating film made of silicon is formed on a surface of a base material made of silicon carbide. In the second film formation step, a second coating film is formed on a surface of the first coating film. In the oxidizing step, the first coating film is thermally oxidized from a surface side to form a third coating film. In the second film formation step, on a part of the first coating film, the second coating film is not formed, and the part is exposed. Alternatively, in the second film formation step, a film thickness of the second coating film formed on the part of the first coating film is smaller than a film thickness of the second coating film formed on a different part.

Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.

Methods of forming silicon nitride on a sidewall of a feature are disclosed. Exemplary methods include providing a substrate comprising a feature comprising a sidewall surface and a surface adjacent the sidewall surface, forming a silicon oxide layer overlying the sidewall surface and the surface adjacent the sidewall surface, using a cyclical deposition process, depositing a silicon nitride layer overlying the silicon oxide layer, and exposing the silicon nitride layer to activated species generated from a hydrogen-containing gas. Exemplary methods can additionally include selectively removing a portion of the silicon nitride layer. Structures formed using the methods and systems for performing the methods are also disclosed.

A method for selectively etching silicon germanium with respect to silicon in a stack on a chuck in an etch chamber is provided. The chuck is maintained at a temperature below 15 C. The stack is exposed to an etch gas comprising a fluorine containing gas to selectively etch silicon germanium with respect to silicon.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a third nitride region. The first nitride region includes Al.sub.x1Ga.sub.1-x1N (0x1<1). The first nitride region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second nitride region includes Al.sub.x2Ga.sub.1-x2N (x1<x21) or In.sub.yAl.sub.zGa.sub.(1-y-z)N (0<y1, 0z<1, y+z1). The second nitride region includes a sixth partial region. The third nitride region includes Al.sub.x3Ga.sub.1-x3N (x1<x3<x2). The third nitride region includes a seventh partial region.