Patent classifications
H10P14/6905
Composition for depositing silicon-containing thin film and method for manufacturing silicon-containing thin film using the same
Provided is a composition containing a silylamine compound and a method for manufacturing a silicon-containing thin film using the same, and more particularly, a composition for depositing a silicon-containing thin film, containing a silylamine compound capable of forming a silicon-containing thin film having a significantly excellent water vapor transmission rate to thereby be usefully used as a precursor of the silicon-containing thin film and an encapsulant of a display, and a method for manufacturing a silicon-containing thin film using the same.
Systems and methods for depositing low-k dielectric films
Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-oxygen-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency less than 15 MHz (e.g., 13.56 MHz). The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.5 and a hardness greater than about 3 Gpa.
Composite substrate and preparation method thereof, and semiconductor device structure
A composite substrate includes a substrate, a high-resistance layer located on the substrate, the high-resistance layer comprising a first low-temperature aluminum nitride (AlN) layer, a high-temperature AlN layer and a second low-temperature AlN layer which are stacked in sequence, and a growth substrate located on a side, away from the substrate, of the high-resistance layer. Under the action of the first low-temperature AlN layer, a tensile stress on the high-temperature AlN layer may be reduced, to reduce a dislocation, and further improve a crystal quality of the high-temperature AlN layer and ensure resistivity of the high-temperature AlN layer; and an element of Al in the high-temperature AlN layer is prevented from diffusing into the growth substrate, to protect the crystal quality of the high-temperature AlN layer and improve a bonding effect between the high-resistance layer and the growth substrate. Thus, stability and reliability of the composite substrate are greatly improved.
DEPOSITION BY ELECTRON ENHANCED PROCESSES WITH POSITIVE SUBSTRATE VOLTAGE
A method for depositing a film includes conducting electron-enhanced chemical vapor deposition with at least one hydride precursor, at least one reactive background gas, and electrons to deposit a film on a substrate with a positive substrate voltage. In an embodiment, the method is a method for depositing a silicon film, including conducting electron-enhanced chemical vapor deposition with at least one Si precursor, at least one reactive background gas, and electrons to deposit a silicon film on a substrate with a positive substrate voltage. In the embodiment, the at least one Si precursor can include Si.sub.2H.sub.6 and the at least one reactive background gas can include H.sub.2.
METHOD FOR MANUFACTURING ZEROTH INTERLAYER DIELECTRIC
Disclosed is a method for manufacturing a zeroth interlayer dielectric, including: step 1: providing a semiconductor substrate subjected to a process of forming a contact etch stop layer; step 2: performing a first deposition process using a HARP process, to form a first oxide layer fully filling a spacing region; step 3: polishing the first oxide layer using a first chemical mechanical polishing process; step 4: performing wet etch to lower a top surface of the first oxide layer and form a first groove at the top of the spacing region; step 5: performing a second deposition process using an HDP CVD process, to form a second oxide layer fully filling the first groove; and step 6: polishing the second oxide layer using a second chemical mechanical polishing process, which is stopped on a surface of a first gate material layer of a first gate structure.
Forming a planar semiconductor surface
A method for producing a planar semiconductor surface includes forming a workpiece that has a carrier substrate, one or more insulating layers, a semiconductor layer, a first etch stop layer, and a second etch stop layer; forming a contact on the workpiece; biasing the workpiece to a second voltage through the contact; etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer; biasing the workpiece to a first voltage through the contact; and etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer to produce a semiconductor device with a planar surface on the semiconductor layer.
Method of forming treated silicon-carbon material
Methods and systems of forming treated silicon-carbon material are disclosed. Exemplary methods include depositing silicon-carbon material onto a surface of the substrate and treating the silicon-carbon material. The step of treating can include a first treatment step followed by a second treatment step, wherein the first treatment step includes providing first reductant gas activated species and the second treatment step includes providing one or more of a first oxidant gas activated species and a second reductant gas activated species.
DIRECTIONAL SELECTIVE FILL FOR SILICON GAP FILL PROCESSES
Exemplary processing methods may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature within the substrate. The methods may include forming plasma effluents of the silicon-containing precursor and the carbon-containing precursor. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor, and etching the silicon-and-carbon-containing material from a sidewall of the feature within the substrate. The methods may include providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber, forming plasma effluents of the nitrogen-containing precursor, and doping the silicon-and-carbon-containing material with nitrogen.
Selectively etching for nanowires
A method for selectively etching silicon germanium with respect to silicon in a stack on a chuck in an etch chamber is provided. The chuck is maintained at a temperature below 15 C. The stack is exposed to an etch gas comprising a fluorine containing gas to selectively etch silicon germanium with respect to silicon.
Semiconductor structure and method for forming the same
A semiconductor structure and a method of forming is provided. The semiconductor structure includes nanostructures separated from one another and stacked over a substrate, a gate stack wrapping around the nanostructures, and a dielectric fin structure laterally spaced apart from the nanostructures by the gate stack. The dielectric fin structure include a lining layer and a fill layer nested within the lining layer. The lining layer is made of a carbon-containing dielectric material, and a carbon concentration of the lining layer varies in a direction from the gate stack to the lining layer.