A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

A process for manufacturing a silicon carbide device from a body of silicon carbide having a back surface, wherein a first layer of a first metal is formed on the back surface of the body; a second layer of a second metal, different from the first metal, is formed on the first layer to form a multilayer, the first or the second metal being nickel or a nickel alloy and forming a nickel-based layer, another of the first or the second metal being a metal X, capable to form stable compounds with carbon and forming an X-based layer; and the multilayer is annealed to form a mixed layer including nickel silicide and at least one of X carbide or a metal X-carbon ternary compound.

A part is adapted to be used in a semiconductor processing equipment. The part includes a substrate and a protective coating. The protective coating covers at least a part of the substrate, is made of silicon carbide, and has an atomic ratio of carbon in the protective coating increases in a direction away from the substrate while an atomic ratio of silicon in the protective coating decreases in the direction. The atomic ratio of silicon in the protective coating is larger than that of the carbon near the substrate, and the atomic ratio of silicon in the protective coating is smaller than that of carbon near the outer surface of the protective coating. A method for making the part is also provided.

A topology-selective deposition method is disclosed. An exemplary method includes providing an inhibition agent comprising a first nitrogen-containing gas, providing a deposition promotion agent comprising a second nitrogen-containing gas to form an activated surface on one or more of a top surface, a bottom surface, and a sidewall surface relative to one or more of the other of the top surface, the bottom surface, and the sidewall surface, and providing a precursor to react with the activated surface to thereby selectively form material comprising a nitride on the activated surface.

A wafer support device according to an embodiment provides a wafer support device. The wafer support device has a support table and a wafer guide portion. The wafer guide portion includes a first chamfered portion and a second chamfered portion. The support table has a support surface that supports the wafer. The wafer guide portion has an annular shape that surrounds the circumference of the wafer supported on the support surface with the central axis extending in a normal direction of the support surface as a center. The first chamfered portion connects an inner circumferential surface and an upper surface of the wafer guide portion, and extends upward from the inner circumferential surface toward the outer circumferential side. The second chamfered portion connects an outer circumferential surface and the upper surface of the wafer guide portion, and extends upward from the outer circumferential surface toward the inner circumferential side.

A method of identifying defects in crystals includes the following steps. A silicon carbide crystal to be identified for defects is sliced to obtain a test piece. An etching process is performed on the test piece. Etching conditions of the etching process includes the following. An etchant including potassium hydroxide is used, and etching is performed at a temperature of 400 C. to 550 C. in an environment where dry air or oxygen is introduced, so as to form etching pits of threading edge dislocations (TED) and threading screw dislocations (TSD) in the test piece. After the etching process is performed, a diameter ratio (TED/TSD) of the etching pits of the threading edge dislocations (TED) and the threading screw dislocations (TSD) observed by an optical microscope in the test piece is in a range of 0.2 to 0.5.

Embodiments include semiconductor processing methods to form dielectric films on semiconductor substrates are described. The methods may include providing a silicon-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include providing an inert precursor to the processing region of the semiconductor processing chamber. The methods may include generating plasma effluents of the silicon-containing precursor, the nitrogen-containing precursor, and the inert precursor. The methods may include depositing a silicon-containing material on the substrate.

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Methods for filling a gap on a substrate with a carbon-containing material are disclosed. Exemplary method includes providing a substrate comprising a gap into a reaction chamber and executing a plurality of deposition cycles. Each deposition cycle comprises providing a first precursor into the reaction chamber in vapor phase and providing a reactive species into the reaction chamber, wherein the first precursor comprises carbon.