Methods of selectively depositing a low-k dielectric film are described. In one or more embodiments, the methods include exposing a substrate to a blocking compound, the substrate including a first surface and a second surface, the first surface including hydrogen-terminated silicon, the blocking compound selectively depositing on the first surface to form a blocked first surface; and selectively depositing the low-k dielectric film on the second surface. Methods of forming an inner spacer layer are described. In one or more embodiments, the methods include pretreating a substrate to remove oxide from a hydrogen-terminated silicon (Si) channel of the substrate, the substrate including the hydrogen-terminated silicon channel and a silicon germanium (SiGe) surface; exposing the substrate to a blocking compound, the blocking compound selectively depositing on the hydrogen-terminated silicon (Si) channel to form a blocked silicon channel; and depositing the inner spacer layer selectively on the silicon germanium surface.

A composite substrate includes a substrate, a high-resistance layer located on the substrate, the high-resistance layer comprising a first low-temperature aluminum nitride (AlN) layer, a high-temperature AlN layer and a second low-temperature AlN layer which are stacked in sequence, and a growth substrate located on a side, away from the substrate, of the high-resistance layer. Under the action of the first low-temperature AlN layer, a tensile stress on the high-temperature AlN layer may be reduced, to reduce a dislocation, and further improve a crystal quality of the high-temperature AlN layer and ensure resistivity of the high-temperature AlN layer; and an element of Al in the high-temperature AlN layer is prevented from diffusing into the growth substrate, to protect the crystal quality of the high-temperature AlN layer and improve a bonding effect between the high-resistance layer and the growth substrate. Thus, stability and reliability of the composite substrate are greatly improved.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first member. The second electrode includes first and second electrode regions. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial region. The second semiconductor region includes first to third semiconductor portions. At least a part of the third semiconductor portion is between the first semiconductor region and the second electrode region. The second semiconductor portion is between the first semiconductor portion and the third semiconductor region. The first member includes first and second regions.

A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

A substrate processing method using a substrate processing apparatus which comprises a process chamber in which a reaction space is formed to process a substrate in which a composite layer pattern having a plurality of first insulating layers and a plurality of second insulating layers alternately stacked thereon is formed, a substrate support unit, a gas distribution unit, and a plasma reactor, the method comprising the steps of: heating the substrate support unit and the gas distribution unit such that a temperature of the gas distribution unit is maintained equal to or lower than a temperature of the substrate support unit; supplying a reactive gas including a halogen-containing gas to the plasma reactor; generating radicals by applying power to the plasma reactor to activate the halogen-containing gas; and at least partially etching the plurality of first insulating layers in a lateral direction selectively with respect to the plurality of second insulating layers by supplying the radicals onto the substrate mounted on the substrate support unit through the gas distribution unit.

Semiconductor devices including dual surface passivation layers are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, a drain access region, and a source access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate electrode is disposed in the gate region of the semiconductor substrate, where the gate electrode includes an asymmetrical source-side field plate (e.g., including a single-step profile) extending over at least a portion of the source access region of the semiconductor substrate.

A method for depositing a film includes conducting electron-enhanced chemical vapor deposition with at least one hydride precursor, at least one reactive background gas, and electrons to deposit a film on a substrate with a positive substrate voltage. In an embodiment, the method is a method for depositing a silicon film, including conducting electron-enhanced chemical vapor deposition with at least one Si precursor, at least one reactive background gas, and electrons to deposit a silicon film on a substrate with a positive substrate voltage. In the embodiment, the at least one Si precursor can include Si.sub.2H.sub.6 and the at least one reactive background gas can include H.sub.2.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Methods of depositing silicon-containing films by plasma-enhanced atomic layer deposition (PEALD) are described and can include one or more techniques to provide a chemical vapor deposition (CVD)-type component.