A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

In an embodiment, a method for nitriding a substrate is provided. The method includes flowing a nitrogen-containing source and a carrier gas into a plasma processing source coupled to a chamber such that a flow rate of the nitrogen-containing source is from about 3% to 20% of a flow rate of the carrier gas; generating an inductively-coupled plasma (ICP) in the plasma processing source by operating an ICP source, the ICP comprising a radical species formed from the nitrogen-containing source, the carrier gas, or both; and nitriding the substrate within the chamber, wherein nitriding includes operating a heat source within the chamber at a temperature from about 150 C. to about 650 C. to heat the substrate; maintaining a pressure of the chamber from about 50 mTorr to about 2 Torr; introducing the ICP to the chamber; and adjusting a characteristic of the substrate by exposing the substrate to the radical species.

There is provided a technique that cleans a member in a process container by performing a cycle a predetermined number of times, the cycle including: (a) separately supplying a cleaning gas and additive gas that reacts with the cleaning gas, respectively, from first and second supply parts among at least three supply parts into the process container, and (b) separately supplying the cleaning and additive gases, respectively, from the second and first supply parts into the process container. (A) and (b) include stopping the supply of the cleaning and additive gases into the process container and exhausting the process container's interior. In at least one selected from the group of (a) and (b) an inert gas is supplied from each of the at least three supply parts at a same flow rate, after the supply of the cleaning and additive gases is stopped and before the process container is exhausted.

A method for manufacturing a semiconductor device with high productivity is provided. The method includes a step of forming a first insulator, a second insulator, and a third insulator in this order using a multi-chamber apparatus; a step of forming a fourth insulator, a fifth insulator, a first oxide film, a second oxide film, and a third oxide film in this order using a multi-chamber apparatus; a step of forming a conductive film; a step of processing the first oxide film, the second oxide film, the third oxide film, and the conductive film, thereby forming a first oxide, a second oxide, an oxide layer, and a conductive layer each having an island shape; a step of forming a sixth insulator and an insulating film in this order using a multi-chamber apparatus; a step of planarizing the insulating film; a step of forming, in the insulating film and the sixth insulator, an opening where the second oxide is exposed; a step of forming a seventh insulator and a first conductor; and a step of forming an eighth insulator and a ninth insulator in this order using a multi-chamber apparatus.

A Low Pressure Chemical Vapor Deposition (LPCVD) technique is provided to produce improved dielectric/semiconductor interfaces for GaN-based electronic devices. Using the LPCVD technique, superior interfaces are achieved through the use of elevated deposition temperatures (>700 C.), the use of ammonia to stabilize and clean the GaN surface, and chlorine-containing precursors where reactions with chlorine remove unwanted impurities from the dielectric film and its interface with GaN. The LPCVD silicon nitride films have less hydrogen contamination, higher density, lower buffered-HF etch rates, and lower pin hole density than films produced by other deposition techniques making the LPCVD coatings suitable for device passivation. A metal insulator semiconductor (MIS) structures fabricated with LPCVD SiN on GaN exhibit near ideal capacitance-voltage behavior with both charge accumulation, depletion, and inversion regimes.

A method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. The stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. The select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. Storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, channel material is formed simultaneously in the upper and lower channel openings. The storage material is removed from the upper channel openings. After the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. Other embodiments, including structure, are disclosed.

A semiconductor device includes a plurality of conductive lines, a protection layer and an isolation layer. The conductive lines are spaced apart from each other. The protection layer conformally covers the conductive lines. The isolation layer covers the protection layer. Ability of the protection layer to endure stress is better than ability of the isolation layer to endure stress.

Disclosed systems and techniques are directed to improving chucking of substrates using stress-compensation beams with multiscale irradiation doses. The techniques include decomposing a profile of a deformation of a substrate into a plurality of harmonics, and identifying, using chuckability reference data, one or more harmonics of the plurality of harmonics having an amplitude above a maximum amplitude capable of being flattened by a predetermined clamping pressure exerted on the substrate by a chuck. The techniques further include determining, based at least on a subset of the one or more harmonics, settings of a stress-modulation beam, forming a stress-compensation layer (SCL) on the substrate causing a modification of the deformation of the substrate, and irradiating the SCL with the stress-modulation beam, wherein the stress-modulation beam causes a reduction of the deformation of the substrate.

A method of forming a semiconductor structure includes forming a conductive structure in a first dielectric layer. A second dielectric layer is formed over the first dielectric layer. A conductive contact is formed in the second dielectric layer. The second dielectric layer is etched to form a recess on a top surface of the conductive structure. A native oxide layer is formed on a top surface and a sidewall of the second dielectric layer, the top surface of the conductive structure, and a sidewall of the conductive contact. A first plasma process is performed to form a first material layer over the native oxide layer by using a first plasma gas. A second plasma process is performed to form a second material layer over the first material layer by a second plasma gas different from the first plasma gas. A spacer layer is formed on the second material layer.